The challenges of double pattering (DP)-based design are looming large to those customers starting to move to the 20 nm technology node.
By David Abercrombie
The challenges of double pattering (DP)-based design are looming large to those customers starting to move to the 20 nm technology node. Of course, much of the fear and trepidation is simply due to it being something new to learn, and the sense of risk that a move into the unknown can instill. Regardless of emotions involved, DP does place new restrictions on physical layout that will invariably lead to new errors to debug during the design process. The most common type of DRC error associated with DP is called the odd cycle violation.
Figure 1 illustrates three polygons that form an odd cycle violation, because each of the polygons is close enough to one of the other polygons that they need to be on opposite colors for double patterning. The red “ring” marker indicates the error to the designer. The challenge of odd cycle violations is that it is impossible to correct all three violations through simple double patterning color assignments, as shown by the coloring examples. All the coloring options result in a violation in which two polygons have the same color when they should be opposite.
Figure 1: Example of an odd cycle DP violation and potential space-based fix solutions
Using basic DP coloring, the only way to fix an odd cycle violation is to increase the spacing between any two of the polygon pairs, as shown. Of course, adding space can cause ripple effects with other layers, and may ultimately increase the size of your layout.
An alternative solution to fixing odd cycle violations is to introduce cuts into the layout [1]. The concept of a cut is to divide one of the polygons involved in the odd cycle into two pieces, and assign one piece one color and the other piece the other color. This changes the odd cycle of three into an even cycle of four. Figure 2 shows a typical odd cycle of three polygons, and three possible cutting solutions that change it into an even cycle of four, eliminating the DP spacing violations.
Figure 2: Examples of cut solutions to change an odd cycle of three into and even cycle of four
With one of the polygons divided into two pieces, the colors can now be alternated in a “legal” manner such that half are on mask 0 and half on mask 1. The final shape of the divided polygon is still targeted to be the one continuous shape on the wafer, but will simply be formed in two parts during the photolithography and etch operations.
However, introducing a cut in a polygon can cause problems in manufacturing [2]. First of all, at these technology nodes, the drawn shape is not exactly reproduced on silicon when manufactured. Even with advanced optical processing correction (OPC) techniques, lithographic “rounding” of line ends causes sharp corners to become curved. This effect means that at the cuts shown in Figure 2, the two pieces would not meet as two straight-edged patterns. Instead, each “line-end” would round, and they would meet at a point, causing an additional resistance in the line, or an open if there was no overlap. For this reason, the two pieces of the polygon must be overlapped at the cut location to allow for lithographic rounding and misalignment and still end up with a continuous polygon. This overlap of each color at a cut location is called a “stitch.” Figure 3 demonstrates these lithographic issues and how a stitch solves them.
Figure 3: Lithographic processing effects on cuts with and without stitching
A properly stitched cut can provide a means of fixing odd cycle violations in DP design without adding space and increasing the design area. However, there are limitations as to where a cut and stitch can be placed in the design. The added stitch cannot introduce new DRC violations. In other words, the two polygons that are created from the original single polygon must both meet all DRC requirements. Figure 4 shows examples for how all the DRC constraints can limit the candidate locations for legal stitches.
Figure 4: Example stitching constraints that limit the placement of legal cuts/stitches in the layout
Manually figuring out where you can and cannot place a stitch can be a daunting task. Automation of this process is essential, and is being provided to designers in the sign-off DRC/DP deck delivered by the foundries that support this approach. Figure 5 shows an example of a 20 nm metal layout that was checked by Calibre® Multi-Patterning for DP odd cycle violations. The top design in the figure contains two odd cycle violations (flagged by the red rings). The orange warning rings identify even cycles associated with the odd cycles that will become part of a new odd cycle error if a spacing-based fix is attempted anywhere the orange rings touch the red rings. The user can attempt to fix these errors by increasing the space at any location where a red ring crosses the gap between polygons and does not touch an orange ring. In the top layout, you can see that the left error has only one spacing location that can be used in a fix, and the right error has two spacing locations that can be used to make a fix. The automated cut and stitching functionality in Calibre Multi-Patterning produced the bottom layout. You can see that the right error was fixed using the circled cut/stitch. Although the left error does not have a legal location to place a cut/stitch that would fix it, the circled cut/stitch has been added to eliminate one of the warning rings and allow a second space-based fix solution for the user.
Figure 5: 20 nm metal layout with odd cycle violations and the solutions provided by stitching.
Some foundries have decided to support the use of automated and/or manual cuts/stitches in DP design, with the goal of providing design density and error minimization, while other foundries have decided not to support cuts/stitches to minimize complexity of design and manufacturing.
What do you think about these two approaches? Is the area savings worth the complexity? Let me know in your comments to this blog. In my next blog, I will look at another difference in design approaches for DP—colorless vs. 2-color design flows.
References:
[1] Kun Yuan; Jae-Seok Yang; Pan, D.Z.; , “Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.29, no.2, pp.185-196, Feb. 2010
doi: 10.1109/TCAD.2009.2035577
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5395742&isnumber=5395722
[2] Vincent Wiaux, Staf Verhaegen, Shaunee Cheng, Fumio Iwamoto, Patrick Jaenen, Mireille Maenhoudt, Takashi Matsuda, Sergei Postnikov and Geert Vandenberghe, “Split and design guidelines for double patterning”, Proc. SPIE 6924, 692409 (2008)
doi:10.1117/12.774104
http://spiedigitallibrary.org/proceedings/resource/2/psisdg/6924/1/692409_1
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Thank you! It was very informative indeed.