Design And Verification Survey Results

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins.

This year, I would like to add some additional highlights and trends that I see from the survey data.

For “What verification technologies will you adopt or change in 2013?”, Lint led with 27% of respondents, followed closely by X-propagation at 26% and CDC at 22%. The 2012 data shows a different mix with CDC leading at 25% followed by both automatic-formal checking and SDC constraint analysis at roughly 22%. My thought on this result is that designers are looking for a set of applications that tackle specific verification challenges, with CDC being a continuing source of concern.

CDC bugs are a problem since they result in late stage ECOs or product re-spins. Year-over-year we see that around 65% of respondents have run into these late-stage bugs.  This is also consistent with a poll that ran at ChipDesignMag.com, which reported 68%.

Why is CDC an ongoing concern? Besides the raw increase in the number of gates and signals in a design, the number of clock domains is continuing to grow. In our surveys we have seen that more than 36% of designs have more than 50 different clock domains, and more than 7% have 100 domains. This combination of design size and number of domains and synchronizers that need to be checked is straining incumbent tools at designers’ work sites.

We also asked if CDC verification is a nice-to-have or a sign-off criterion. Again the answers have been very consistent at about 70%. This confirms that they have been burned in the past by CDC bugs and need to use design automation tools to avoid getting burned again. The new technologies in our Meridian CDC product tackle these challenges head-on.

What about the other application areas for verification?

We asked “Are you using automatic formal analysis currently?” and 41% said yes. While we didn’t drill down for any specifics for the kind of analysis they were using, we did ask a follow-on question “When doing full-chip verification, are you still finding block-level bugs?” More than 85% reported yes, which leads me to conclude that more exhaustive verification needs to be done at the block level and automatic-formal tools are a good candidate for that. Our announcement on Feb. 26 of the new release of Real Intent’s Ascent IIV tool is latest answer to this continuing need for early verification of RTL bugs at the block-level.

While RTL linting has for a long time been standard design practice there is still dissatisfaction with designers. When asked “Does your current Lint tool have limited usage because of speed, capacity, or poor reporting?” we saw more than 60% say yes. This leads me to conclude our Ascent Lint product is answering a need in the marketplace.

Finally, I would like to mention the results from our query “What X (unknown) issues affect your designs?” The most popular response was X-optimism at 36%, followed by X-pessimism (26%), power management (21%), and the need to reset all flops to clear Xs (16%). Our Ascent XV product has some new technologies that address these issues and we expect to see growing customer success with our offering.

Overall, I see that designers are still looking for better ways to find bugs early in their design cycles and to sign-off critical issues such as CDC.  We look forward to sharing our newest innovations at the Design and Verification Conference (DVCon) in San Jose, March 3-5. Come by our booth #802 at the exhibition and see how we can help meet your verification challenges.