Design Solutions For 20nm And Beyond

The consumer’s insatiable demand for greater performance, a shrinking form factor and extended battery life, all while continuing the trend for lower end user cost is the driving force behind the semiconductor industry’s rapid evolution to ever smaller process geometries.

As with many of the previous process geometry shrinks, there will be the usual concerns about the increase in design complexity, the management of power consumption and the need to get products out in a timely fashion. However, while there are perceived capacity, power and performance benefits at this node, without careful consideration of the design tools, these benefits could easily be removed by the myriad pitfalls of over designing, unnecessary guard banding, poor manufacturing yield or simply taking too long to get the chips designed and hence missing that all-important market window of opportunity. The large increase in cost for designing these IC’s will limit adoption in the early years to the highest volume applications where competition for the lowest cost, highest performance AND lowest power is fierce, and the potential cost of failure is enormous.

For the first time, the significant impact of manufacturing techniques required for 20nm and the sheer size and complexity of the geometries involved will have a dramatic impact on every aspect of the EDA tool chain and the related design/CAD flows currently in use. Therefore, an ever closer interaction between these tools is needed to ensure that the overall product goals can be met. To manage the risk and ensure success at this node, tighter collaboration with leading EDA vendors will be paramount, and the ramifications of not aligning to the optimum flow will be numerous.
Many early adopters are already partnering with Synopsys to leverage emerging capabilities and the close interoperability found throughout the Galaxy Implementation Platform of tools. This new node compared with 28nm, promises a doubling of logic densities while delivering a significant 30% improvement in performance or 25% lower power at the same operating frequencies.

This white paper will highlight the major challenges of building ICs at the 20-nm node, will hopefully help you identify the tool and design flow changes required and ultimately show you how the Synopsys Galaxy Implementation Platform meets and exceeds these new challenges.