Designs Getting Squeezed

It’s taking longer to get chips manufactured these days. At advanced nodes, there are more steps on the photomask side as a result of double and multi-patterning. And at established nodes, an explosion in demand for chips aimed at automotive and —particularly on the industrial IoT side (IIoT)—has created demand-driven constraints.

However, longer manufacturing times don’t equate to longer market windows. In fact, market windows actually are shrinking slightly, particularly in new markets where first movers can win larger market share. The result is that design teams everywhere are beginning to scramble to figure out where efficiencies can be added into the design process, what can be fixed after tapeout in software, and snapping up new tools where it makes sense to speed up the process.

“Capacity is the big issue at the higher (older) nodes,” said Taher Madraswala, CEO of Open-Silicon. “So far we haven’t seen a time-to-market issue, but we are buying capacity. We’re basically becoming a bank for our customers to grab capacity.”

The assembly and test side is still unconstrained, he said. “The fab is the bottleneck. They are working on this and adding capacity, but not fast enough.”

Open-Silicon isn’t the only one that sees a potential problem. Mike Gianfagna, vice president of marketing at eSilicon, has been watching the same trend unfolding.

“The time it takes to get a chip manufactured has gone up,” said Gianfagna. “At advanced nodes, there are more mask steps and it takes longer. There’s a lead-time to print and there are more masks, and they’re using the same equipment they’ve been using, so the throughput goes down. The cycle time in the fab hasn’t changed, but the mask data/prep/dispatch to manufacturing is up. A lot of organizations use the same teams for new and older nodes, too, so while they get impacted at the front end less at older nodes, the whole process slows down. You have to do more and more work to keep everyone in lock step.”

A day here, a day there
Chipmakers have been feeling this time pinch for some time. “We are always aiming for shorter time to market,” said Tadahhiko Yamamoto, chief specialist at Toshiba. “But it’s not so easy to cut time to market.”

The message is resonating loud and clear at EDA companies. Tools are being updated to do more, and to do it all faster. That’s evident in the expansion of the “shift left” concept, which initially was created as a way of speeding up physical synthesis. The concept is now being applied throughout the design flow, including software.

“Shift left implies moving everything to the left,” said Aart de Geus, chairman and co-CEO of Synopsys. “Software needs a shift left, as well.”

De Geus said the shift left in the design cycle includes everything from debug and coverage to analog/mixed signal, verification IP, simulation and emulation. But increasingly it also means more pre-configured subsystems, more IP that is integrated with software, and more pre-testing. And it includes faster tools so that individual segments within a design flow can get the job done more quickly. What’s worth noting is that the design cycle does appear to have some flexibility and room for improvement, or at least the motivation for handling more complexity more quickly. It’s much harder to compress the time spent in the mask shop and in manufacturing.

“There are two main problems,” said Anirudh Devgan, senior vice president for the Digital and Signoff Group at Cadence. “One is that the fab time is longer, so if you’re on a one-year schedule you’ve lost two months because the fab time is taking longer. The front end takes longer. The back end (verification) takes longer. And what gets squeezed in the middle is the implementation. The second problem is the price of re-spins is very high in terms of market window. You used to build a re-spin into the cycle, but getting it right the first time is more and more critical.”

There’s a new wrinkle in this, as well. Since the mid-1990s, the trend has been for OEMs, or systems companies, to specialize on designs and turn over the chip design through manufacturing to fabless chipmakers. That worked well for the past couple decades because it allowed the OEMs to get exactly what they want more cheaply, and to play off the fabless companies against each other on price, performance, and for the past several process nodes recently, power.

But as chips become more complex, large OEMs such as Apple, Google, Facebook, and a host of others have begun bringing designs in house, particularly in the mobile market, which has prompted many of these fabless companies to seek their fortunes at older process nodes in the IoT or automotive market. The challenge is that more parts need to work together than in the past. This plays better in the modern version of an integrated device manufacturer—one that uses semi-custom IP, even if it isn’t developed in house, and more iterative interactions with the foundry—than a well-defined specification. The reason is that the spec may need to be tweaked throughout the design cycle or in future iterations.

John Kibarian, president and CEO of PDF Solutions, cited one example where a chipmaker won a socket in a very high-profile product, but when the device was released on the market the part had issues. “The vendor traced it back to failures on the chip. The part had glitches. So they swapped over to a competitor’s chip. But that part had problems, too. The reason was that the problem was in the process, and they both bought wafers from the same foundry.”

IP
IP is supposed to help simplify things, and in many cases it does. But IP also is a differentiator, and big systems vendors are now leaning on IP developers to tweak the IP for their own purposes.

“The big issues that can result from that are timing-related,” said Kurt Shuler, vice president of marketing at Arteris. “You can create the most awesome SoC, but you may not know if it’s manufacturable until the very end. Some customers don’t plan on a re-spin, so they either get it right—or right enough—and then fix the rest in software. But you have to be really good at product planning, meaning you have a mask set at this time, work in another area at another time. And even if you get it right, if you misjudge demand high or low there’s a problem.”

First-time silicon success has turned into a mantra in the design industry. All of the Big Three EDA CEOs talk about it regularly. Case in point: In his keynote at the Synopsys User Group (SNUG) this week, de Geus cited chips that now contain more than 10 billion transistors. “You have to get it right the first time,” he said. “When you do that many zeroes you have to have six sigma.”

Every major EDA company pitches it as an essential outcome these days for controlling costs and hitting market windows—and for selling more tools. But at least part of the success strategy needs to be a flexible methodology and better application of the tools a company already has.

“You need better models earlier, so you can do system analysis work,” said Drew Wingard, chief technology officer at Sonics. “But you also need to build in escape hatches—extra runtime configurability. It’s basically fixed margin that you can deploy when things come out in ways that you didn’t expect. These are arbitration circuits that can be reprogrammed at runtime.”

Wingard said that we have long passed the point with complex SoCs where failure is an option. It’s simply too expensive and costly in terms of time. “We are seeing more and more designers who are less and less convinced they can get it right the first time. We’re also seeing much more willingness to build in margin to deal with that. In the old days it was much more of a struggle to get people to pay for margin. Now it’s table stakes for the design process.”

Different architectures
Another approach that holds the promise to speed things up, once the kinks are worked out, is stacking die, and that has gained much more attention over the past year as companies begin hammering out the best way to approach this.

“The IoT will use a lot of multi-device packages—basically what used to be called multi-chip modules,” said John Park, business development manager and methodology architect for Mentor Graphics‘ System Design Division. “There are still big gaps here in the tools, though. One involves connectivity management, where you have three or four die that include an interposer, discrete element and other components. This used to be done on spreadsheets. A second area that needs to be addressed is that you need view everything together in a single database, including the package. Right now there is no design rule check or electrical check in the tools, so you stitch it together with connectivity and optimize or path-find.”

Some large chipmakers say privately they already are looking at the chip and the package simultaneously. One vendor said the ultimate goal is a single layer package to it can view the chip and the package together. A second vendor uses several packaging options and then chooses the right package, which already has been well studied and characterized.