DFM And Multipatterning

Experts at the table, part 1: Colors, no colors, and something in between; how long can multipatterning survive and where are the alternatives; collaboration becomes critical; the role of EUV.

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Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and verification at Cadence; and Soo Han Choi, a member of the senior staff for foundry R&D in Synopsys’ SoC design group. What follows are excerpts of that conversation.

SE: Patterning is becoming much harder at 14nm and beyond. Is it becoming too expensive, too complicated or too unwieldy?

Lin: We’ve had a collaborative effort starting with double patterning. We need even more collaborative efforts. Some like it colorless, some like colors, some like both. That’s creating confusion in the design community. As an industry we need to lay down a road map and give pros and cons for each approach to guide the designer. DFM will have to be color-aware.

Abercrombie: It’s not too expensive or complicated, although the number of players will be fewer. We’ve already seen that trend. You have to be able to justify this financially. At this point, the alternative EUV is a lot more expensive than doing triple patterning or quadruple patterning. It’s still just an economic decision. We keep moving. We’ve found a way to do it. It is all about collaboration. We create software solutions to problems that seem insurmountable. It’s more than just a tool or a process. It’s the design flow and the methodology, and getting on the same page with that is very difficult for one foundry—and even more difficult across multiple foundries. We worked it out at 20nm and we’ll work it out at 10nm.

Lai: Part of the challenge is we do need to support everything, and everyone has a slightly different point of view. And everyone has slightly different secret sauce for double patterning. From a vendor standpoint, we have to deal with it, whether you want it to be fully colored, fully uncolored, or something in between. Maybe some colors have to be locked while other colors need to be unlocked, because people are doing things in slightly different ways. There is a lot of room for problem solving. Not everyone is interested in going this route. It is more expensive. But it’s also a source of differentiation. If you’re one of the smart, nimble companies doing this, you can take advantage of it. You can create better designs, have better control of your parasitics, lower area, better power. So you may want to continue with what you were doing before, or you may want fully interactive coloring so you know exactly what’s going on.

Choi: The EDA vendors need more collaboration with the foundries. The foundries need to understand the problems faced by EDA vendors. Cooperation is more important.

Kye: If you look at the theory of double patterning, linear scaling is at 50%. But if we work together, it can be cheaper because you can save 60% of area. We have a rule to deal with. So double, triple and quadruple patterning will be cheaper as long as we are able to manufacture and design for less money. And if there is another solution, such as single patterning with EUV, that will be an even cheaper solution. But our view isn’t just that double patterning, triple patterning and quadruple patterning are expensive or that mask costs are too expensive.

SE: Will EUV actually make that much of a dent? If the insertion point is 7nm, we’ll probably need double patterning with EUV.

Kye: It definitely will be cheaper in theory and better, but most of the manufacturing is not about double patterning. It’s integration and vertical direction, which is overlay-dependent. For that we are working on self-aligned double patterning that is less sensitive to overlay.

Lai: If EUV does become available and it’s cheaper and it gets you where you want to go, people are going to jump on it.

Abercrombie: It’s not a wholesale decision. It’s a layer-by-layer decision. It’s already to the point where you won’t do double patterning or triple patterning on every layer. You’re not going to do self-aligned double patterning or EUV on every layer, either. It will be determined by cost and, from a process integration standpoint, whether the model is robust. If you’re an EDA vendor, you support it all because you don’t know what’s going to win.

Lin: The cost is shifting from manufacturing to the design side because of the complexity. How long can the designers of EDA flows handle all of this complexity? For 10nm and 7nm and below, some foundries are moving from fully colorless to color.

Abercrombie: We’re proud that we can bring value to a solution that doesn’t have another alternative. It’s more cost effective than the other solution. It started at 65nm with OPC. You wouldn’t be doing this at 40nm if it weren’t for some kind of EDA solution that could make litho work.

SE: Should we have more exacting designs in the first place, maybe with fewer metal layers, saving cost at the other end?

Lai: We need to do both. Our customers are telling us to make it correct by construction with more exacting design, more exacting design rules, just to make it work. Then there are other customers that still want full control.

Abercrombie: It’s not just pitch. It’s also vertical. It’s 3D stacks. It’s supporting integration of different chips into the same package. More metal layers, in a way, is just more integration. Instead of reducing the pitch on one metal layer you add another layer. It’s another solution to the pitch problem. We do it all and we support it all. We work on multipatterning and the 3D stack.

Lin: It’s the density, the balancing of the color, adding more color—and we’ve had trouble already with two colors.

Kye: We’re working on the design side, the technology side and the EDA side all together. The majority of the concerns involve connectivity of the transistors to the package that’s a vertical insulation. How many more layers are going to be there? How do we integrate? We solved congestion by introducing more layers and more MOL (middle of line) layers. We’re seeing more and more innovation. Even with quadruple patterning we’re going to limit it to certain layers to make sure that connectivity is there.

SE: What’s the realistic limit in terms of how many layers you can have where you have to stitch together different masks?

Kye: The connectivity is not necessarily limited by the stitching or pitches. Power is driven by RC. We will continue as long as the connectivity is there. That’s why we’re going to a larger and larger pitch. We can 8 or 10 metal layers with the larger pitches. If that’s feasible, we will do it. But we also have to make sure the wire is not too narrow or too short. A short wire can be at shorter pitch, a longer wire can be a longer pitch. We’re using wire lengths in innovative ways.

Abercrombie: That’s why we’re working on silicon photonics. It’s a whole new approach. It’s not a numbers problem. It’s an RC problem. Or it’s a transmission line. We’re investigating silicon photonics communications.


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