Double Patterning: Sharing the Benefit and the Burden

By David Abercrombie

Share and share alike! Our mothers always said it was the right thing to do, and it seems that this ideology is now coming front and center for double patterning at 20nm and below. As we continue to shrink the metal pitch from node to node, we also push the lithography k1 lower and lower, since we are currently stuck with 193nm/1.35NA scanners. When k1 dropped below 0.6, the scanner alone could no longer resolve the images on the wafer, and new EDA software had to be developed to compensate for the lost resolution (Figure 1). This software began with rule-based optimal proximity correction (OPC), and as we continued down the curve, we added model-based OPC, sub-resolution assist features (SRAF), and similar techniques to keep up with Moore’s law. But at 20nm, k1 dips below 0.25, and a whole new kind of technology, double patterning, will be required. As Figure 1 illustrates, the trend continues with 14nm requiring triple patterning or spacer assisted double patterning (SADP). In fact, even if the initial EUV scanner capability arrives for 11nm, we may still need double patterning for some layers using EUV.

Figure 1: Advanced lithography k1 & software trend

Figure 2 shows how the increase in resolution capability was enabled at each node. For the 90, 65, and 28nm nodes, most of the increased resolution came in the form of new scanner capability. For the 45 and 20nm nodes, almost all of the increased resolution comes from software-based solutions. Kudos to the EDA industry, but why does this matter to the designer?

Figure 2: Percentage of increased litho resolution delivered through hardware & software by node

It matters because some of this software and extra work is “creeping” into design. In actuality, a little of this manufacturing creep has been going on for some time now (Figure 3). This migration of manufacturing requirements into design started with a few suggested activities in 65nm, such as recommended rules compliance, lithography checks, and critical area analysis (CAA). Then, at 45nm, some of the lithography simulation checks became required. Jump ahead to 20nm, and now double patterning, lithography simulation, and smart fill are required, and CMP simulation, CAA, and recommended rules compliance are heavily promoted.

Figure 3: Migration of manufacturing requirements into design

Although both manufacturing and design benefit from the development of all of this optical processing software, up until 65nm, nearly all the direct cost and effort of using it was isolated to the manufacturing side. While some of the extra expense was passed to the design side in the form of increased wafer cost, it was pretty much indistinguishable from other cost components. For 20nm, there will be an increase in wafer cost directly attributable to the cost of double patterning. Figure 4 shows the IBS estimates for early adopter wafer costs across nodes.

Figure 4: Wafer price trend

Prior to 20nm, you can see that wafer prices trended to approximately a 25% per node increase. Starting at 20nm, that increase jumps to around 60% per node. Most of this increase comes from the extra process steps required to do double masking and etching, as well as the double patterning software the fabs will have to use in mask preparation.

However, what really shines the light on “share and share alike” is that at 20nm, designers will also be required to purchase new double patterning software, and do additional work in the design layout and verification to enable the actual double patterning processes in the fab. Like the earlier manufacturing tools, the double pattern checking and decomposition capability requires a whole new software engine under the hood to properly analyze the layout. But unlike the earlier layout issues, double patterning violations can be much more pervasive, and fixing them is mandatory, not just recommended.

Don’t fret too much about all the new cost and effort, though. Remember the “share and share alike” motto. Just keep reminding yourself that if it wasn’t for double patterning, the fabs would be forced into buying unproven, infancy-level EUV tools with $100 million dollar price tags and 1 wafer per hour throughput, and your wafer cost would be increasing by much more than 60%. So in the end, we all share a little burden, but we all get a big benefit. Do you think the design community is aware and prepared to take on this new cost and effort for 20nm designs?

In my next blog, I will focus on some of the new solutions being developed to assist in the challenges of debugging double pattern layout violations.