EDA Startups At DAC 2025

The 62^nd DAC showcased numerous new exhibitors in 2025, including tool and IP providers, design services firms, and component marketplaces. New EDA startups, in particular, had a robust showing, with entrepreneurial engineers seeking to tackle the increasingly complex challenges facing modern chip design with fresh approaches.

AI was a strong theme throughout the show, with companies of all sizes touting the ability for agents to boost design and verification productivity. But beyond that, many of these new companies are focused on enhancing collaboration, enabling engineers and teams across an organization to work together seamlessly and share knowledge in new ways.

Semiconductor Engineering spoke with some of these EDA startups to learn more about their solutions.

Bronco AI
Bronco AI focuses on AI for design verification regression analysis. It aims to tackle the repetitive work and key motions that a DV engineer performs when starting the debug process, such as checking finite state machines, interfaces, and common failure patterns.

Based on a high-level description of a debug process, the company’s AI tool generates a detailed playbook that documents the individual tasks in that process. This playbook then can be followed by Bronco’s AI agents to automatically assess regression failures and generate a ticket for the engineer with further details.

In addition to freeing up time that would otherwise be spent figuring out why each regression failed, Bronco sees the use of playbooks and AI agents as a way to reduce organizational friction. With a set of steps that are defined and followed, an engineer doesn’t need to continually consult with a project’s expert designer or DV engineer about basic or repetitive tasks. And when they do need to ask for assistance, they have detailed information about the state of the issue and the steps that have already been taken. This also creates documentation that can be used to record institutional knowledge and streamline the process of onboarding new members.

ChipAgents
ChipAgents develops an agentic AI chip design environment. By deploying AI agents for EDA workflows, the company says it can provide a 10X boost RTL design, debugging, and verification productivity. Its chip design environment enables designers to transform concepts into precise design specifications using simple language prompts, analyzes and generates RTL design specs and code, auto-completes Verilog, automates the creation of testbenches, and autonomously verifies and debugs design code through real-time learning from simulations.

“We have created a system of AI agents, purpose-built for chip design and verification. Rather than forcing users to conform to a fixed abstraction or methodology, the technology integrates directly into the flow — understanding design intent, parsing complex specs, generating and validating RTL, suggesting micro-architectures, synthesizing assertions, and even explaining waveform anomalies,” William Wang, CEO of ChipAgents, told Semiconductor Engineering.

“Rather than replacing the existing toolchain, it can be augmented with intelligent agents that generate RTL and testbenches from spec, interpret waveform outputs, debug tracebacks, and adapt prompts to internal codebases and naming conventions,” Wang said. “That can dramatically reduce iteration time and manual overhead for both design and DV engineers.”

Wang said this reduces manual iterations in UVM test environments by identifying constraint and coverage bottlenecks early. “Instead of the traditional waterfall flow, teams are adopting agentic AI workflows to reduce iterations. For example, they might begin with a micro-architecture plan and evolve both the design and verification assets in tandem, using this technology to maintain the design intent in natural language alongside the implementation. It also helps new team members quickly get up to speed by querying design history conversationally. Across our early deployments, we’ve observed a 10X productivity boost in verification and debug workflows, along with measurable improvements in onboarding efficiency and developer satisfaction.”

DSM Pro Engineering
DSM Pro Engineering is developing a complete RTL-to-GDSII project management system for chip designs that aims to improve collaboration between project managers and engineers.

It stores all project metadata in a programmatically accessible SQL database, eliminating the need for makefiles. This database includes the design itself, as well as the actual build flow, running tasks, individual tools, their licenses, distributed machines, disk arrays, tool scripts, metrics, and reports. From a web-based interface or command line, a user can track all aspects of a design and flow, as well as launch and orchestrate AI agents for specific design tasks.

ITDA Semiconductor
ITDA Semiconductor makes a drag-and-drop visual designer for SoC system design. Its no-code solution enables power control, clock, and design for test (DFT) systems to be built and optimized from a GUI, then generates all design outputs for synthesis, including RTL, UPF, SDC, and lint waiver files. Cross-checking of a precise software framework and hardware model ensures output accuracy.

ITDA says its approach enables the creation of designs with dozens of power and clock domains for fine-grain clock gating and power management in less than a week, with automatic generation of DFT inserted power controllers, clock controllers, and OCC insertion points. Its DFT tool supports the configuration of any hard IP test structure at the RTL stage, allowing users to define DFT scan chains, access networks, and hierarchy without low-level scripts, and enables GPIOs to be dynamically reconfigured even during test mode.

MooresLabAI
MooresLabAI is developing an agentic AI framework for accelerating verification. Its verification agents can take an IP-level, block-level, or SoC-level design and generate the entire UVM testbench from scratch, along with scoreboards, assertions, coverage reports, and all the test cases for the design.

The company says its approach can significantly reduce verification time, shortening overall time-to-market. The solution supports simulators from the major EDA companies as well as open-source tools.

In the future, MooresLabAI plans to expand to agents that develop specifications and assist in writing and debugging RTL.

Oboe Technologies
Oboe Technologies provides an FPGA-based emulator designed to be as simple, cheap, and collaborative as possible. It integrates with existing CI/CD platforms and requires a single small configuration file to enable teams to hunt complex bugs, quantify the performance of real software workloads, and evaluate candidate architectures in parallel through a centralized interface that brings the lab bench to the computer screen.

Oboe also offers its waveform viewer as a standalone tool to enhance collaboration with commenting, third-party software integrations, and the ability to track changes. On top of the viewer are AI tools to help group waveforms and debug.

Rise Design Automation
Rise Design Automation aims to raise the level of design and verification beyond RTL and overcome the knowledge barriers that have prevented high-level synthesis from being widely adopted. The company says its approach can shorten the time from architecture to implementation, making it faster to add new functionality such as accelerators or develop IP variants.

The company offers a multi-language, multi-abstraction high-level synthesis, verification, debug, and analysis suite of tools. Users can begin with a high-level design, describing functionality and algorithms using SystemVerilog, C++, or SystemC. This high-level description is then synthesized into RTL, which is optimized to meet the design specifications.

For engineers who aren’t experts in those languages, Rise’s generative AI advisor uses language models to help generate code at the untimed behavioral level, which the company’s tools then turn into a timed representation.

In addition to design, Rise says its approach significantly improves simulation speed, enabling awareness of physical aspects, functionality, and correctness earlier in the design process, when it’s easier to make changes and iterate on a design. This also shortens the time from architecture to implementation.

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