EDA…Or Something Else?

The Design Automation Conference is almost here. That major focal point for the EDA industry where we gather to explain the present, predict the future, have a bunch of serious meetings and maybe a little fun, too.

Some companies will stage an incremental update of their strategy and others will outline a major new strategy. This year, Atrenta will be talking strategy, with some announcements and a whole lot of demos to back it up. We’ll talk at length about SoC Realization—the part of the SoC design process that sits between system level design and silicon implementation. Pictorially speaking:

We’ll also have a little fun. For the first time, we have a trailer for DAC and a spokesperson, of sorts. If you have a little over a minute, check out this video.

I digress, this is starting to sound like a sales pitch and that’s not the point. The diagram, above, borrows a market segmentation that was originally proposed by Cadence a little over a year ago in their white paper entitled “EDA360, the Way Forward for Electronic Design.” One can certainly debate some of the concepts in that white paper, but the basic premise that SoC design is composed of a system design component, a silicon implementation component, and a piece in the middle that ties the two together does make a lot of sense.

Silicon realization is what pays the bills at most EDA suppliers today. That’s where the heavy lifting of synthesis, place & route, extraction, verification and tapeout occurs. It’s also an area that has become highly competitive and which is seeing some consolidation. We’ve all heard the refrain – chip complexity is going up and tapeouts are going down, as are the number of foundries in the world. Does this mean that someday there will only be a few monster chips being built by a few foundries? That’s quite unlikely. The market will find a way to differentiate.

Re-use will help, especially as we move from IP re-use to subsystem re-use. New technology advances like 3D stacked die will also help. The complexity of these new SoCs, or whatever we will call them, will demand design at a higher level of abstraction. It will simply be too hard to design any other way. So, the regimes of system realization and SoC realization will become the new battleground where end users compete for the next big thing.

But what about the foundation of EDA—what about silicon realization? Let’s start with an observation. Silicon realization flows are becoming more tuned to the target process. That tuning involves implementation flows that are lithography- and variability-aware, among other things. So the question is this: If there are to be only five (or fewer) foundries in the world, why don’t they each just buy a silicon realization flow and take it in-house? That will result in a well-calibrated, predictable and robust path to silicon. In that world, old EDA becomes part of the manufacturing process, and new EDA becomes, well, something else. It’s time for a new name.