Efficient Hierarchical Verification For Low Power Designs

By Susantha Wijesekara and Himanshu Bhatt

Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for accuracy of results and performance. While black box flow is best for performance, the full flat runs give the best quality of results as full design is available for checks. Adopting a new flow, Signoff Abstraction Model (SAM), for hierarchical low power verification can provide guaranteed QoR by retaining enough logic at the sub-module level to deliver much better runtime performance at the SoC level compared to flat runs. Additionally, this flow enables the SoC integrator to focus on top level violations and integration related issues and not worry about violations deep inside the hierarchical blocks, since the block owners would sign-off their blocks after review of the violations. With this efficient solution there is 8X-15X runtime performance gain and reduced memory consumption as compared to the full flat verification, while not losing any QoR, and greatly reducing reduce the turnaround time (TAT) during low power verification sign-off.

Traditional hierarchical verification flows vs. new technology

Figure 1: Comparison of hierarchical low power verification flows

• In traditional approaches, partitions are completely black boxed – signoff not guaranteed
• New flow generates a boundary accurate SAM model for the partitions
• Guaranteed QoR – Proven with additive and subtractive QoR flows
• Up to 15x performance seen on netlist designs

Figure 2: Black Box flow vs SAM flow

Low power hierarchical verification methodology
In this new hierarchical flow, blocks that are integrated into the SoC will need to be abstracted first using a low power static checker, such as Synopsys’ VC LP solution. During abstraction, the hierarchical instances and net connections that are not needed for top verification activities are removed and a model will be dumped into a new HDL file. This HDL model can be loaded into the SoC instead of the original block to do the SoC verification. Benefits of using this flow include less memory usage, improved run time and focused violations (violations reported will be mainly related to top level integration).

The following diagram shows how hierarchical designs can be abstracted and used in hierarchical blocks to achieve the same QoR as flat runs but with improved performance and reduced turnaround time.

Figure 3: SAM hierarchical flow

Characteristics of the abstract model
The abstract model is generated in such a way that it will only contain the minimal set of logic needed for top level verification, which provides a light weight model compared to the original block netlist. This will help to improve the runtime of the static checking tool during design read as well as LP checking.

During abstraction, the tool models necessary logic for complete verification. As a result, the designer does not need to specify any special constraints on the boundary ports of the blocks. Since all the required logic is modeled there will not be any missing violations during the SoC verification.

Validation of the results
This new hierarchical verification flow will ensure that there will be no loss of LP violations. All the violations reported in top level flat run will be reported in either block level flat run or Top+Model run.

Results and conclusion
The table below shows the runtime and memory gains for some designs on which the SAM flow was enabled

Next-generation SoCs with advanced graphics, computing, machine learning and artificial intelligence capabilities are posing new unseen challenges in low power verification. Traditional LP hierarchical verification flows are not scaling up for new designs that are being taped out with billions of transistors and large number of power domains. New tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and at the same time ensure that there is no loss of QoR.

Himanshu Bhatt is a senior staff applications engineer with low power verification team in the verification group at Synopsys. He has 18+ years of overall experience spanning EDA and Semiconductor industry including ASIC design and verification using various verification methodologies like eRM, UVM, CPF, UPF, formal, equivalence checking. He is currently working as a Low Power Verification Specialist to help designers define and refine their low power verification flow.