EM Analysis At Advanced Nodes

Going forward, a very different method of EM assessment can be proposed if we look at interconnect reliability from the position of its functionality, when the failure of the interconnect means its inability to function properly. The two most important functions of the chip interconnect are:

1. Providing connectivity between different parts of design for proper signal propagations (signal circuits), and
2. Delivering the necessary amount of voltage where it is required (power supply chain).

While the degradation of the resistivity of individual segments of interconnect circuits can ruin both of these functions, the potential impact of EM is quite different in the case of degrading the power supply chain versus degrading the signal circuits, due to the types of electrical currents employed in these two cases. Signal lines carrying bidirectional or unidirectional pulsed currents are characterized by very long time to failure. The absence of failure in this case is caused by a repetitive increase and decrease of the mechanical stresses at the segment ends, caused by atom accumulation and depletion due to interaction with the electron flow, and the healing of possible micro-voids initiated at these ends if the stress exceeds critical level.

In contrast, power lines carrying unidirectional currents may fail in a much shorter time, due to continual stress buildup under EM action. Because of this, we can conclude that EM-induced chip failure happens when the interconnect cannot deliver the necessary voltage to any gate of the circuitry. It also means that loss of performance, which is a parametric failure, should be considered as the practical criterion of EM-induced failure, rather than a catastrophic electrical breakdown or short. It is clear that the structure of the power grid, which is characterized by a high level of redundancy, can affect the kinetics of failure development. Indeed, due to this redundancy, the failure of some number of interconnect segments does not necessarily result in an unacceptable increase in the voltage drop in the grid. More accurate and less pessimistic full-chip EM assessment and MTTF prediction require development of new methods that take into account the grid structure and redundancy. Chip-scale MTTF should be determined as that instant in time when a fraction of failed segments increases the voltage drop above the acceptable level.

This type of EM assessment assumes a prior knowledge of current densities and temperatures in each segment across interconnect. The complexity of extracting these distributions is exacerbated by an uncertainty in workload occurring in modern chips. The complex multi-modal behavior of these chips means the power dissipated by different blocks is dependent on the modes of operation. That, in turn, means that current densities and temperatures in different interconnect segments must be estimated for different workloads, and these estimations must be used for prediction of MTTF for different scenarios, including worst-case conditions for voltage drop.

Effect of residual stress variation on EM assessment
An additional problem that must be addressed in the development of a robust methodology for full-chip EM assessment is an absence of reliable physics-based models for void/hillock initiation and growth that cause a time-dependent degradation of the segment’s electrical characteristics. The currently employed Blech limit (for filtering out immortal segments) and Black’s equation (for calculating MTTFs for segments characterized by known current densities and temperatures) cannot handle an experimentally demonstrated dependency of MTTF on residual stress. Across-die variation of residual stress requires that the Blech “critical product” and Black’s activation energy and current density exponents be considered as layout-dependent variables, rather than experimentally-determined constants. Due to the observed dependency of n and on j and T, the Black equation that was calibrated at the stressed conditions (elevated j and T) cannot be used for the accurate estimation of MTTF at operating conditions. Strictly speaking, these inter-dependences of n and on j and T undermine the validity of the Black equation at advanced technological nodes. Segment-to-segment variation of the initial stress makes the “critical product” filtration less straightforward as well.

Once we establish this new definition, we must compare the (j x l) product for each interconnect segment with the now-variable “critical product”

where S(i) init is the residual stress existing inside the considered interconnect segment before EM stressing is applied. The “critical product” is not a constant anymore, but a variable that depends on segment location relative to all possible stress sources. In the case of chip-scale EM assessment, this means both the currently required assessments of temperature and current density, and the proper assessment of residual stresses, must now be performed. A new physics-based MTTF compact model, which is free of all discussed flaws related to the Black-Blech formulation, is required. This model should provide an analysis or look-up table containing the dependency of void-nucleation time and the following kinetics of the segment resistance on all major design and process parameters, as shown in Table 1.

Table 1. Void nucleation time inside a 100 mm length line as a function of the current density and temperature of the stressing test. Upper-right corner demonstrates the conditions for segment immortality. Leftmost column shows the conditioning temperature responsible for thermal stress-induced voiding.

Summary
A new approach for full-chip EM assessment should provide a robust methodology for EM hotspot checking, and the capability for more optimistic prediction of EM-restricted current density for future technological nodes. This new methodology would include existing EM analysis, as well as new methodologies for the accurate calculation of corner current densities and temperatures in the presence of workload uncertainties. A dependable methodology for calculating the across-interconnect distribution of residual stress caused by a sequence of the process steps and following stress relaxations will be required. Solid criterion for failure based on increased voltage drop above acceptable levels that is caused by EM-induced segment resistance degradation, taking into account grid redundancy, must be developed and validated with chip performance measurements.

To view part one of this series, click here.
To view part two of this series, click here.