Experts At The Table: Are We Cool?

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: At 28nm we have clock gating, power gating, dynamic voltage switching, power islands, power states, and a whole bunch more engineering miracles. Are they working?
Castagnetti: The methods are there. In some occasions they have been proven. But do we know which methods to use for which designs? That’s where the challenge is today.
Low: We are already deploying all of these tricks to our design since 65nm nodes. We are leveraging all we can, and it is increasingly important as the complexity of logic keeps increasing as we head down to next technology nodes.
Brotman: There are a number of things we are trying to do in the physical space. We’re providing a small amount of power savings with things like 3D devices. We also try to provide a lot of things in the flows to show people how to conserve power. But the biggest way to achieve good power savings is on the system level.

LPE: But some of the most interesting power savings developments recently are out of the process side, right? There’s Intel’s Tri-Gate, better atomic-level control on doping, and then there’s a push into fully depleted SoI.
Brotman: You have to use all of those things. But there are things that can be done even on planar chips at the system level that can impact power.
Castagnetti: There’s still that hope that process technology will come to the rescue, but we have to realize that is unlikely. Everyone is talking about moving to the next node to save dynamic power, and now leakage is coming down. But as long as you’re doubling your transistor density every node your power density will go up and therefore the issues you have to solve from a power delivery and power management and thermal point of view are here to stay.
Low: At 28nm, we started seeing an increasingly finer granularity of VT options to combat leakage. However, the higher the VT class, the higher threshold voltage of a device. This limited our engineers to lowering our operating voltage while maintaining acceptable performance. The Tri-Gate concept is certainly the right direction to optimize both dynamic and leakage power.

LPE: One of the hardest concepts to understand is that there is no such thing as off. Does it really matter if you turn something completely off?
Castagnetti: If you keep switching on and off then potentially you can burn more power. But customers are trying to make more use of power-island types of approaches. There is another component, as well. It’s very expensive to do a complex chip today. You want to leverage that across multiple platforms, so you want to maximize your power efficiency across those platforms by being able to turn things off when you don’t need them.
Low: You have to be careful when constructing power islands to the power delivery network that there isn’t any hidden path between different power domains. That’s very important.
Brotman: The system itself has to be efficient when you’re shutting things down and bringing them back up. Too often that’s going to burn more power.

LPE: So how do you figure out what to shut down and what not to shut down? An optimum configuration depends on who’s using the device because it varies from one user to the next.
Castagnetti: Even in the wired space we try to determine the use model of that device and what makes sense to turn on and off. For instance, do I make use of memories with low-power modes when I don’t know how often they will be accessed? You need to have that understanding. There’s room for the EDA industry to have analysis tools in this space to guide the end user toward that. They should have the end application and end user in mind.
Low: In the mobile space, our software knows when a device is active and what’s being used, and it can power down the unneeded logic. You can write software to enable the system to stay awake, shut down after a certain period of time, or go into sleep mode when you want.

LPE: Are there issues around whether some of these devices can actually be manufactured?
Brotman: We’re not seeing those. We do have to define how devices are going to be used, and in the tool flow we need to predict when to power them down and power them up. When people are doing designs and implementing certain functions, we want to make sure they work.

LPE: Will we see more restrictive design rules to ensure that?
Brotman: There certainly are more design rules as you go down in process geometry. A few of them may make it into interpath parasitics. We’re definitely going to see those, but I don’t think the restrictive design rules will directly impact the things we do to control power.
Castagnetti: It’s not necessarily power-aware restrictive design rules.
Low: On the design side we need to pay a little more attention to the overall power delivery network. As we head down to advanced technology nodes, performance degrades significantly as we lower operating voltage. We have to look at the package-level power network extraction along with those in silicon to make sure we’re not overly designing our chips.

LPE: As we get down into advanced nodes there’s a lot more third-party IP and software. Is all of this stuff power-aware? And if it isn’t, how to we get it to be more power-aware?
Castagnetti: When you start mixing and matching parts, you have to start thinking about whether they are all in line with your power-management. That’s being power-aware from an overall system point of view. And sometimes the IP doesn’t lend itself to aggressively dropping the voltage. Memories might stop working, or they might stop working reliably.

LPE: But if you have a piece of software and it’s being used part of the time, that software should be able to understand it may not need to power up quickly for a certain application or it needs to power up very quickly. Does that happen now?
Castagnetti: It does in some circumstances. There is energy-efficient Ethernet. You have a plug in your laptop that you probably don’t use very often because you’re connected wirelessly. The energy-efficient Ethernet standard has implemented handshake signals so you can bring that PHY back up when you plug in a cable and start moving traffic. The industry is starting to see value in those kinds of things.
Low: We have power-based switching where the software enables a port only when it’s being used. That helps to conserve energy.