Experts At The Table: Nice To Have Vs. Need To Have

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: Where is the most activity? What node?
Rajendiran: Over the last three years it has undergone a transition. At 180nm everyone looked to 130nm and then they were all looking at 90nm. The foundries started introducing processes sooner and sooner. It used to be about three years between nodes. Then it became two years. Between 90nm and 65nm it was really only a year. It confused everyone because the expense was going up. The IP companies had issues. Then the economic downturn hit. We saw a resurgence of a lot of designs going to 130nm again instead of 90nm and 65nm. There are companies that have chips and are thinking about taking what they have and combining them into an MCM (multi-chip module). It may not even be their own chip. They may be combining it with another company’s chip.

LPE: So it’s going in two directions?
Rajendiran: Yes. Some companies are looking at MCMs. Others are looking at 40nm and 28nm. There is a lot more risk, so people are really thinking out of the box.
Levia: Everyone looks at it from their perspective, but that can be really different depending upon the market they’re in, the size of their company, the geography they’re in. The economy comes into play whether you’re in China or the United States or Canada. What you’re trying to accomplish is very different.

LPE: In the past, when we pushed to the most advanced nodes, you were dealing with one or two problems. Now you’re dealing with all of them at each new node. How does the cost equation affect everything?
Levia: Fabless companies and IDMs, whether they’re moving to the next node or staying at existing nodes, haven’t always figured out up front what the compounded complexity will be. That may be in the form of verification or the design or integration or packaging, functionality, reliability or DFM. The demand that puts on the EDA industry is to come up with very quick solutions to second- and third-level integration problems. It also puts pressure on the cost function. We are expected to participate in that cost reduction. The problem has exploded, but the price of the phone has gone down and the revenue to the chip provider has gone down slightly, so you’re expected to take a haircut. It’s a problem, but it’s an opportunity for the companies that can automate difficult steps. These steps may be very mundane. It may be power estimate at the right time, or power-aware debugging at the right time. It may be DFM or DRC at the right time. You need to understand what is taking a lot of time and whether you can automate it. It’s shifting ground, though.
Gianfagna: The synthesis place and route flow is getting less interesting. Will you have a better product because you use synthesis place and route from Cadence vs. Synopsys? I don’t think so. Will you have a successful product because you chose the right IP or number of processors? Yes. The value for differentiation is moving up the stack, past the synthesis place and route flow to better IP reuse, better debug and better planning. There is a shift to put more effort on the front end because if you spend $1 on the front end you can save $3 on the back end. If you can eliminate a two-week place and route, that’s worth a lot. You also don’t need as many tools, but that’s a secondary benefit.
Rajendiran: At every handoff point you need certain things. But the industry has undergone so much pressure they don’t always think this through. You need clean deliverables at each point. There is value at every step to help with the cost of ownership. You may put a heat spreader into the package, but that may cause more harm than good. People don’t necessarily think that way, though. Given everything you’re doing, is that the right solution? Some companies are better at understanding the big picture. When you have a customer and they’ve established a methodology that they really think through, that’s usually better than a startup at understanding it. It isn’t the tools, the IP or the package. At the end of the day the product has to come out on time.
Buric: For most customers to move to signoff from the spec and all the way down is not always possible. I have seen designs people have finished and missed off spec by a few percent and they had to throw it away because it was designed to be on a PC board. There was no room for error. It doesn’t matter whether it comes from process, bad calculation or bad estimation. The industry is moving to very accurate analysis and signoff on an architectural level, and then at each level try to meet those specs. We are spending more and more on accurate modeling, and EDA companies are taking more spreadsheet functions to make high-level analysis as accurate as possible. On top of that, you can’t afford to move from a plastic package to a ceramic package because it costs too much. From the other side, I’m seeing more and more end users or system houses to provide a spec without getting involved in the design at all. They don’t see the value of design. They see the value of the box.
Gianfagna: That’s a perfect distillation of the process. The signoff need is unquestioned. There’s a long checklist of timing closure and design processes and electrical rules check for the gate-level netlist. That’s moving upstream. You want rigorous signoff earlier and earlier. The ultimate is a spec-level signoff, which will take awhile.
Levia: Let me inject a little bit of reality into this. Calibre is still not done at any high level—definitely not at RTL. But Calibre is signoff and it is doing quite well. The reality is that it’s only successful because it is offering a step that is absolutely necessary and is incapable of being accomplished any other way. You cannot do it by hand. At 28nm and 22nm, there are more rules but it’s still more complicated. There are 3D effects and the tools are conditional.
Buric: That started at 65nm.