Finite Math
Solving power problems at future nodes will require a change in mindset from start to finish.
In his keynote speech at the Mentor User-To-User conference yesterday, Sameer Halepete, Nvidia’s vice president of LSI engineering, made a very interesting point. At all levels of computing, from smartphones to the data center, the power budget is fixed, and the old ways of addressing it aren’t working.
What that means is that there will not be a single solution to reducing power. It can’t be fixed anymore just with a new process technology or by shrinking feature size. Instead, it has to be conceived at the front end and addressed in small increments at every step of the design process all the way through to manufacturing.
This raises several challenges:
- Power cannot have a significant impact on design time or cost or there won’t be a market for the chips. That means new tools, new understanding of how power will affect designs at every step of the flow, and new flows that are power-aware, with an emphasis on physical verification and yield using low-power processes.
- Power issues must be dealt with holistically. Because power budgets are flat from one generation to the next, any increase in one area will require decreases in others. Moreover, they will have to be properly timed—which is no simple task—to avoid creating hotspots. Turning off one area of a chip without considering when another area is active and generating heat can cause all sorts of unwanted physical effects.
- Tools will be needed to fine-tune designs based upon power, and they need to be able to test them with the same granular approach. As Halepete noted, on, off, power-down, power-up states can be interlaced much more densely using automation than even the best designers can do today—and that’s the lowest hanging fruit.
Power has been recognized for several nodes as being a global issue for design. It is now a global issue for entire systems, whether it’s a smartphone or a car. Moreover, it spans everything from initial architectural conception to manufacturing and final test. But what’s changing is that it now also has to be dealt with by everybody, at every stage, and inside of every tool.
Ed Sperling
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Ed Sperling is the editor in chief of Semiconductor Engineering.
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