First Look At USB 3.2

I’m super excited to write about and show to you the world’s first USB 3.2 demonstration.

Go watch the video first and then read the rest.

USB 3.2 hardware and software setup
We implemented our USB 3.2 Device and Host in the HAPS-80 FPGA-Based hardware prototyping platform.

The platforms use USB PHYs, which are implemented in a FinFET process node. Our FinFET PHYs run at 10 Gbps per lane. The lane bonding allows for two lanes to achieve USB 3.2 speeds.

The Device platform consists of the HAPS FPGA platform and USB PHY. The HAPS platform connects to a PCI Express to a Linux PC. The Device is configured as a Mass Storage device, like a USB 3.2 SSD or USB 3.2 Flash Drive. To reduce latency, a small amount of RAM on the FPGA board is used for the local storage. The Linux PC can run on a Mass Storage driver, the Client or Device side firmware stack.

The Host platform is a similar HAPS 80 platform which connects to a PHY board. The HAPS connects to a PCI Express cable to a Windows 10 PC. The FPGA board connects to the PC like a USB 3.2 xHCI Host add-in card. The Windows 10 PC is running standard out-of-the-box Windows drivers.

We used a standard Type-C connector on both platforms and a standard off-the-shelf Belkin USB 3.1 Type-C cable that you can buy at any retail store, like your local Target.

Running the demonstration
In the video, you’ll notice that the transfers are running throughout the filming, the entire 60 minutes we recorded the video. So when we start the video, we’ve already initiated the HD_speed benchmarking application. We maintained the USB 3.2 speeds throughout the demonstration while we recorded repeatedly the introduction, hardware description, the demonstration, B-roll footage, and all.

Why is this important?
Synopsys believes in investing to ensure high quality products for their customers. By participating in committees, building IP early, and continuously testing it to ensure the best results, we learn about every small detail that comes with proper USB IP implementation. Our hundreds of engineers have 1000s of years of engineering experience building controllers and PHYs. By authoring the specifications, building quickly, demonstrating first, and revising quickly, we can build and deliver IP that meets the latest USB IP specifications.

Synopsys continues to invest in USB and high speed SERDES to benefit our customers. This first USB 3.2 demonstration is part of Synopsys’ continuous leadership in USB IP.