First Silicon At 14nm

By Ed Sperling
The first 14nm test chips are beginning to roll out the door from foundries, and companies are beginning to trumpet their success. But before anyone pops the champagne corks, there are some caveats.

First of all, what most people are billing as 14nm chips are actually mostly 20nm. They are readily willing to concede that point, settling on 16nm, but the reality is that it’s a hybrid of technologies from various nodes. The real 14nm would require triple or quadruple patterning, and so far no one has created test chips for public viewing using multi-patterning.

Second, for all the talk about how straightforward this was, there is still much work to be done to optimize the test chips. At this point it still isn’t possible to make meaningful comparisons between these 14nm test chips and fully depleted SOI at 28nm or stacked die using any nodes. And while it’s possible to do the double patterning, there are many new issues arising at this node that still have not been addressed.

Finally, the tools that were developed at previous nodes do work at what’s being labeled 14nm, but it’s uncertain how they will be affected at 10nm, which is considered the next major process node. Whether that node will truly be 10nm, or whether it will be a collection of technologies from different nodes is uncertain, but almost everyone agrees it will be more difficult.

What node are we talking about?
What typically defines a process node is the gate length or the distance between features on a device. For example, the distance between two transistors on a 20nm process node would be 22nm/20nm. For 14nm, you would expect it to be 14nm. But it actually is based on a 20nm back-end-of-line (BEOL) process technology—the interconnect, low k and metallization portion—and a 14nm “modular” fin. http://semimd.com/blog/2012/08/16/foundries-tip-h,ybrid-finfet-flows/

While this may sound confusing, it allows the foundries to extend their 20nm investment in equipment and processes. For the foundries, this is a very smart move. FinFETs offer a huge benefit in terms of controlling current leakage more effectively—basically the ability to shut off a device when it’s not in use with better control of the gate—but finFETs weren’t supposed to hit the market until 14nm. The problem is that the 22nm/20nm process node requires double patterning, so migrating there is a lot more work with a higher NRE and less payback in terms of performance and power than a node with finFETs, so the foundries created a hybrid.

Rather than pushing to the real 14nm node—which likely will require multi-patterning because of a long series of delays in getting EUV lithography out the door, as well as a new manufacturing flow and new equipment—the foundries have combined 14nm fins with 20nm BEOL processes. (There is even talk now of moving finFETs to 28nm, according to sources, where double patterning is not required.)

“The next node will bring lots more changes,” said Michael White, senior product marketing manager in Mentor Graphics’ physical verification group. “The spacers will be double patterned, which is much more complex. So you have two masks to do the imaging that look very different from what the designer draws. There will be DRC and other challenges with SADP, and there will be so many possibilities you won’t be able to solve them with math. That will severely limit the types of designs that are allowed.”

What still works
Still, the first chips produced using this hybrid node approach are encouraging. Tools that were developed for 20nm continue to work at what is now being called 14nm.

“There weren’t too many things we didn’t expect,” said Kevin Kranen, director of strategic alliances at Synopsys. “We started working on this with TCAD three years ago, so we were able to hammer out what to include in the model and what’s in the extraction.”

Synopsys also had a team working with Chenming Hu, the UC Berkeley professor who co-invented the finFET.

“There are certainly a lot more design rules,” said Kranen. “But there also has been a focus on design rules for preferred layers, so you may only see metal in some directions.”

All of that is aimed at keeping costs down and design time to a minimum, allowing companies to extend their investment in tools with a minimal learning curve.

In addition, much of the change wrought on the design side by finFETs is hidden from the design engineering teams. “The details of the finFET are buried,” said Mark Murphy, strategic program director for Cadence. “The standard-cell libraries are being developed that the PLLs and memories will need to take advantage of. And there are still big challenges on the custom side. But the basic concepts have been proven in silicon.”

Nevertheless, no one would call this an easy transition.

“This certainly is not a breeze, said Dipesh Patel, executive vice president and general manager of the Physical IP Division at ARM. “The big challenge is that everything is being defined as we do the test chip. That requires flexibility because the PDK will change. We will have to update libraries, memory compilers and tape out again. Still, from 20nm to 14nm there is nothing that caught us by surprise. For people working with double patterning, they already are quite familiar with this approach. The bigger issue was going from 28nm to 20nm because of the double patterning. But what we don’t know yet is what kinds of frequency and power savings we’re going to get, and whether that will be enough for some companies to move to 14nm.”

He said that data probably will not be ready until the end of the year.

What isn’t fully baked
There are lots of other kinks to work out, too, both on the design and on the process side.

From the design side, there are increased worries about physical effects such as electromigration and noise.

“With finFETs you can do voltage scaling and lower the supply voltage because you have much finer control of the channel,” said Aveek Sarkar, vice president of product engineering and support at Apache Design. “But once you go out to the board and package, that noise (from higher frequencies and lower voltage) can cause problems, and as a designer you may not have looked at the dynamic voltage and questioned what effect it will have on the noise. We’re also seeing a problem with electromigration. Between FD-SOI and finFETs, there are different rules and they’re complex. Electromigration seems straightforward enough, but the drive strength is higher with finFETs and the wires are smaller at advanced nodes. You will have to analyze all of this in more detail than it has been done before.”

Robert Hoogenstryd, marketing director for design analysis and signoff tools at Synopsys, said new extraction models also are needed. “This is going to be an iterative process,” he said. “You can’t just enhance the device models, because how do you define a finFET? We also need to figure out which things we leave to the extractor and what goes into the SPICE model.”

On top of that, only a piece of the double patterning issue really has been resolved, and on the manufacturing side the fill around transistors is becoming more complicated.

“The positioning of fill is very complicated for the front end,” said Jean-Marie Brunet, product marketing director for litho-friendly design and DFM at Mentor Graphics. “We’ve already had a lot of yield issues at 40nm and 28nm due to filling around the transistor. The symmetry of the fill can have a tremendous impact on the Vt (threshold voltage) of the transistor. If you fill it with a lack of symmetry, the threshold may not be what you expected.”

He noted that at 14nm, there also is a problem with density balancing. While the masks may be balanced for color, there is also a problem with densities of what’s on each mask. “That’s where we are now,” he said.

Finally, there also needs to be more exploration done up front in these designs as the tools and processes close in on commercial viability. “To make that happen we need good libraries and calibration data,” said Mike Gianfagna, vice president of corporate marketing at Atrenta. “This is no longer just about functional feedback. We also need parametric information.”