The recent acquisitions by Cadence, Ansys, Mentor and Synopsys point to a much more power-aware future.
It’s hard to judge things in isolation, but a continuum of acquisitions in the low-power area is proving just how important power considerations have become to hardware and software design, verification and manufacturing flows.
Over the past couple of years acquisitions by Synopsys in the virtual prototyping arena, and Mentor Graphics in the test and embedded software area, have included power-related components. Even Cadence’s acquisition of Altos Design has a power component. But the most recent two purchases—Ansys’ proposed acquisition of Apache Design Solutions and Cadence’s purchase of Azuro—are all about power.
The good news/bad news is that the solutions provided by Apache and Azura are becoming too important to ignore, but not always easy to integrate into existing flows. They’re also too risky to leave on the table in case another company buys them because power management is now considered a competitive edge. Moreover, it’s likely to remain that way for at least the next decade.
For Cadence and Ansys, the goal is more useful information based on a combination of more details and the ability to abstract those details upward. Azuro takes the concept of an ideal clock and an implementation and turns it into an accurate measurement for routing—something that is proving essential at 32/28nm. Cadence claims it can achieve 10% to 15% improvements in system power and several times that number in clock-tree performance by using a better algorithm. And for Ansys, the addition of a chip-package-system approach to power is a critical part of modeling at 45nm and beyond.
The question now is what other companies can offer a power advantage in the flow, and whether there will be new startups in that arena to fill the void as an exit strategy becomes more apparent for investors.
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