Exclusive Data: Design investigations focus on even lower-power chips as industry moves to next generation of embedded processors
Everyone seems to be on a low-power kick, from the ASIC/ASSP world to the growing market of low-power embedded processors and SoCs. But what do the actual numbers tell us about the future trends for such low-power designs?
One way to answer that question is to look at the result of architectural tradeoff studies currently being performed by chip designers. (See chart below) A causal glance at these results for total chip power investigations, which are precursors to actual design starts, suggests that interest in the lowest power designs is trending off.
That’s what seems to be happening for designs with total chip power budgets below 0.11 watts. But a closer look reveals that ASIC designers are performing architectural explorations for future chip projects in the 0.25-to-1 watt and 1.5-to-4 watt power ranges. This makes sense, as the chip industry is just on the cusp of a new wave of low-power embedded processors and SoCs designs and applications whose current target power consumption is at about 5 watts.
The numbers are significant as they represent the architectural tradeoff from almost 1,000 unique design investigations. Still, it is difficult to separate all the market influences that affect this aggregated data. A future report will attempt to filter out these influences by cross referencing other data points, such as targeted end-market applications and more technically oriented data (i.e., gate counts, metal layers, etc.)
For now, though, the data supports what the market place is saying—that low-power designs below 5 watts are growing.
(1) Does not include FPGA design starts. This data is part of the annual “Chip Design Trends Report.”
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