Fulfilling 3D-IC Trade-Off Analyses (And Benefits) With An AI Assist

As we walk around with supercomputers in our pockets and work at desks on even more powerful supercomputers, a lot of processing has moved to the cloud. As a politician described, this can be problematic on a day when there are no clouds in the sky. The world discovered the truth of those words when Crowdstrike struck on July 19, 2024. System designers who spent years balancing power, performance, security, cost, and reliability would have traded everything to avoid that zero-day failure on that day.

As systems designers, we strive to minimize the cost, area, weight, and power consumption of a system while trying to achieve the desired performance predictably over a specified lifetime of operation — all within strictly defined operating conditions. As Gordon Moore himself described in his seminal 1965 paper, we now live in the “day of reckoning,” and now that we have hit the economic limits of monolithic designs, advanced packaging based 2.5D and 3D systems are becoming the only viable solution for most advanced chip designs. The disaggregation of monolithic designs into heterogeneous components, or chiplets, adds additional layers of complexity to our trade-off analyses when designing a system.

AI can and already is playing a big role in helping end users find global, optimal solutions across multi-variate problems, relying on tools capable of multi-physics analyses. AI optimization engines allow us to take into consideration secondary and tertiary effects (snowball effects). For example, when doing reliability analysis of aging circuits, we can additionally look at the effect of an aged circuit on performance, the associated performance boost required (throttle), and additional aging effects due to throttle itself.

Multi-die packages, especially within industries focused on an open chiplet economy, add additional considerations for ‘security in chip’ architecture and design. Chiplets need to be authenticated and tested, and that requires the use of encryption and authentication in a bare-metal stage where no SW/FW drivers have been loaded yet onto the chip. This will likely lead to changes to on-die ROM programming sequences, where the programming will now need to happen at wafer-level.

Small machine learning (tiny-ML) inference models could potentially replace in-line encryption engines, possibly making use of an embedded key within the test patterns to authenticate the chiplets and, thus, not require changes to established industry practices.

As we shrink the 3D interface pitch below 15 µm, use of sacrificial pads is necessary for wafer level probes. However, several factors may force chip designers to one day forego wafer probes altogether. These include the loss of defect and parametric yield coverage resulting from the use of sacrificial pads, the increased test time due to a limited number of sacrificial pads, and higher costs. To test or not to test will be each project engineer’s question to grapple with. AI can help in multiple ways; for example, helping reduce test vector size without reducing coverage, performing failure predictions based on circuit topology and underlying manufacturing technology, and more.

AI can help with workload distributions when considering on-device versus cloud processing. The latter has a very large impact on latency (user experience) and power (data movement). AI is better at identifying tasks and time allocations based on the behavior patterns of the end user and the end device.