The Genealogy of DFM

By David Abercrombie

Family histories are all the rage these days. With the advent of online databases, what was once a difficult and expensive task is now accessible to anyone with Internet access. Not only can you investigate census data, immigration records, and military service records with ease, but some sites also allow you to access information compiled by other site members. All of a sudden, finding out about your great-great grandparents is just a click away. The information hasn’t changed, but the methods of compiling and accessing it have.

Design for manufacturing (DFM) has a genealogy, too. It didn’t just emerge one day as a fully formed technology, and it isn’t a static, unchanging process, either. What we call DFM today is merely a point in a continuum of our ongoing attempts to understand and control the processes that create integrated circuits.

The forebears of DFM come from the manufacturing world: statistical process control, quality assurance, continuous improvement, operational analysis. All of these disciplines address specific aspects of the process of starting with raw materials and resources, and creating finished products and services in an efficient and profitable manner.

Design rule checking (DRC) is the heritage of DFM. When you set out to create something new, the first thing you have to do is prove it can be manufactured. At the start, the semiconductor industry had to determine the basic construction requirements for building ICs. This works, that doesn’t—information was accumulated and refined until the first design rules and corresponding design rule checks were created.

But once we passed 180nm, DRC alone just wasn’t enough. Chips could still be built, but non-linear effects introduced in the sub-wavelength fabrication meant yield and performance were inconsistent, and optical process correction (OPC) applied at the foundry could no longer fix all the yield-limiting configurations. We had reached the point where minute variations of the equipment and processes in manufacturing were affecting the quality of the final product. And getting good chips “some of the time” just wasn’t good enough.

Figure 1. Errors introduced by manufacturing variation Source: GLOBALFOUNDRIES, 2010

Layout modifications were sometimes the only solution, which pushed the responsibility back into the design and verification flows. So the family tree of DFM began to grow, as we moved beyond the pass/fail limitations of design rules to enable designers to implement the “best” layout possible for a design and node. The first order of growth manifested as additional branches on the verification tree with an ever-growing list of design analysis and optimization tools and methodologies:

• Critical Area Analysis (CAA)—identifies random defect hotspots (areas in a design susceptible to shorts and opens caused by dust particles landing on the wafer during production)
• Critical Feature Analysis (CFA)—assists designers in “shrinking” designs to fit smaller nodes, and enables designers to find and make adjustments to susceptible configurations to compensate for the known, but unpredictable, variations during the manufacturing process that can cause a “DRC-clean” design to fail to meet performance or yield expectations.
• Litho-Friendly Design (LFD)—simulates the results of lithography processes on a design to identify configurations that are susceptible to lithography defects and assists designers in finding the optimal resolution.
• Chemical Mechanical Processing (CMP) Simulation— simulates the results of CMP processes on a design to identify potential planarity, fill and density issues, and assists designers in finding the optimal resolution.
• Equation-Based DRC—extends the ability of DRC to check complex multi-dimensional, multi-component configurations by using complex equation characterization.
• Pattern Matching—enables designers/foundries to define problematic configuration patterns, then analyze designs to identify and correct/remove any such pattern occurrences before manufacturing.
• Smart Fill—combines density analysis with automated filling algorithms based on CMP simulation data to determine the optimum filling strategy with the minimum number of fill shapes.
• Double/Multiple Patterning—for designs at 20 nm and below, DP/MP enables designers to “split” the design into two or more parts for the production of multiple masks, enabling the manufacture of smaller, denser layouts.

This list, while by no means complete, illustrates one important aspect of DFM—it isn’t a single or a static process. DFM has evolved (and continues to evolve) as the yield-impacting issues change with the technology nodes. Figure 2 demonstrates this expansion of manufacturing analysis and correction into the design flow.

Figure 2. Migration of manufacturing requirements into design

The second order of growth occurred via the continual improvement of the data from the foundries that feed these tools and methods. Even though DFM is performed primarily by the design side, the effectiveness of any DFM technology relies on the knowledge of the foundry’s process results and the transference of that knowledge back to the design teams through the DFM tool suite and configuration data. This is not a one-time effort. The foundries not only invest significantly in the process experiments and testing for each technology node, but they continuously improve these techniques and expand these efforts in each successive node.

One company that provides an excellent model of ongoing commitment to DFM is GLOBALFOUNDRIES. They have been working over three generations now to continuously improve their DFM solutions by enhancing the DFM solutions they already offer, and expanding their set of offerings with each technology node.

For example, GLOBALFOUNDRIES has been providing Calibre CFA-based DFM tools longer than any other foundry, but they continue to improve on this offering with each node. Their newest manufacturing and analysis scoring (MAS) technology is seamlessly implemented as part of our physical verification run, and integrated into the result viewing environment to provide layout designers with a prioritization strategy (yield score-based). The MAS technology greatly facilitates the application of the recommended rules, enhancing not only quality of physical layouts, but also overall productivity. Andy Brotman, Vice President of Design Infrastructure at GLOBALFOUNDRIES says, “The MAS scoring methodology, based on Calibre CFA, in conjunction with the rest of the Calibre DFM platform, assures that third-party IP certified by GLOBALFOUNDRIES is resistant to manufacturing variability. Likewise, the same platform allows customers to evaluate the IP they develop themselves for their designs, reducing the risk of late stage problems that can lead to late products or slower than expected yield ramps.”

In their DFM-aware yield analysis flow, GLOBALFOUNDRIES uses test data from digital semiconductor devices that have failed manufacturing testing to perform layout-aware failure diagnosis with EDA test tools that provide information such as defect classifications and suspected defect locations. Using their MAS deck in conjunction with EDA tools that combine recommended rules analysis with CFA, GLOBALFOUNDRIES identifies features of the layout that have higher sensitivities to manufacturing variability and feeds this data to the test tools to identify and understand systematic yield loss, and determine if this yield loss is associated with known DFM-sensitive layout structures.

GLOBALFOUNDRIES also continues to add to their DFM offerings. For example, their DRC+ technology uses a pattern-based DRC technique that identifies potentially yield-limiting lithography patterns while maintaining significant performance improvements over full lithography simulation approaches. To quote Andy again, “Foundries use Calibre early in technology development to validate new process design rules, and to determine the specific patterns that require tighter design rule constraints. In the case of GLOBALFOUNDRIES, these rules and patterns are then transferred to our mutual customers in the form of DRC+ decks that integrate rules and patterns into a consistent, high performance verification environment. “

These are just a few of the latest DFM technologies developed by GLOBALFOUNDRIES. What’s important about them, or any DFM technology, is that the knowledge and needs that drive their invention are cumulative. The results from production of the previous node, combined with the lessons learned during new node development serve as the catalyst for new and enhanced DFM technologies.

The final order of growth in the DFM genealogy lies in the hands of the design users. The best tools with the best data will do no good in improving the yield of designs unless used pervasively and effectively by the design teams. As mentioned earlier, DFM is not a one-time event or a static process. Design teams cannot expect to get maximum benefit the first time they try to use these advanced tools and methods, or only by using them at the end just to “see what happened.” Design teams need to devote time and resources to learning the best ways to use DFM tools in their design flows. They need to commit to a long-term process of learning, improving and expanding their DFM processes, and seek out ways to use them earlier and more often throughout the flow to ensure optimization all along the design process flow.

The process for designing a chip should be no different than the process of making the wafer. Foundries don’t just measure quality at the end. They take quality measurements at every step of the process, and continuously tweak their process tools and methods to get the highest-yielding output they can. Design organizations should do the same. DFM can provide those quality metrics and additional tools to help optimize designs at every node and technology.

Who knows what the next DFM technology will be? Who knows what the next best practice for using these tools will be? Not me. But don’t be the one to stop the lineage on your branch of the family tree.