Getting Low-Power IP Integration Right

By Ann Steffora Mutschler
When it comes to integrating multivendor IP, power concerns dominate the challenges that engineers face. To get it right however, there are definitely questions that should be asked when considering which IP to use, along with techniques to manage power complexity.

When choosing IP, the following points should be considered:

1. How mature is the IP being sold? Has this IP taped-out in silicon? What process and foundry?
2. Or, if the IP is mature, how many customers are shipping ICs using this IP?
3. Does the IP design team have high-speed design experience using deep sub-micron CMOS technologies with low supply voltages?
4. Are there any customers that have used or are now using this IP? If so, can you contact them for reference and to find out if there were any serious problems with the IP?
5. How was this IP verified? Has it been certified by any independent standards or compliance body?
6. What are the current errata? Is there a plan to fix the current bugs? What is the vendor’s willingness to share such errata?
7. What is the vendor’s track record in the industry?
8. What level of support is the IP vendor willing to provide? Is the vendor willing to offer services to customize the IP for the application?
9. What level of integration support is needed? Are there any special process options required, for example deep NWELL, thick metal for inductors, MiM capacitors or varactors?
10. Has the IP been tested for ESD and latch-up robustness? Are ESD guidelines provided?

“Unless the IP being purchased is mature, it may contain bugs,” stressed Navraj Nandra, director for product marketing of analog/mixed-signal IP at Synopsys. “Due to the increasingly complex nature of IP, before any purchase is made the first step in doing due diligence on third-party IP is to determine the impact of the current bugs (and any other errata) on the intended application. Some bugs may only be present when specific features or configurations are enabled. If the bugs do affect the intended application, it is important to get a written commitment and schedule for their correction.”

Balancing performance and power
A significant aspect of the engineering effort occurs very early in the design process, when tradeoffs are made to balance power and performance. “Earlier on in the flow when you’re assessing macro-architecture and micro-architecture changes, it’s not a direct balance, but later on when you’ve fixed the micro-architecture you tend to see that it is definitely a balance,” noted Pete Hardee, director of solutions marketing at Cadence Design Systems.

“One of the biggest mistakes we see is to have a solution that is really trying to optimize for timing and what that does is try to eradicate skew in the clock tree. It will buffer not just the critical paths but lots of paths to get the maximum performance. There are many ways of deciding not to do that and only buffering the absolute critical paths with the faster, low-voltage threshold but higher-leakage buffers. You want to use those very sparingly and let the non-critical paths use the high-threshold voltage, low-leakage buffers. Basically, don’t try to fix a timing problem where you don’t have one. The same thing applies to the clock tree. You don’t have to eradicate skew everywhere to get adequate performance. It helps to have tools that are optimizing for timing and power needs at the same time rather than try to optimize for timing and go back after the event for power. We find that that doesn’t work that well,” he explained.

From Synopsys’ perspective, there is no compromise here. “You need the lowest power and best performance,” said Nandra. To this end, he noted that Synopsys supports all the popular interface and analog IP titles, with DDR as one such example. (http://synopsysoc.org/theeyeshaveit/2010/04/six-ddr-protocols-in-one-phy-not-for-softies/)

Further, finding the performance and power balance has a lot to do with the knobs and switches available in the silicon. “For a particular situation, finding the right set of those knobs and switches is, I believe, the art form,” said Ken Brock, director of physical IP marketing at Virage Logic. “We try to make those as easily accessible to designers as possible and so by releasing multiple variants—and again you can have covering all of the processes such as in 28nm TSMC for example they have an HP process and an HPL—the low-power version. Each one of those processes has three to four full-voltage thresholds that allow you to trade off power for performance. And then there is another dimension, which is gate length. That gives you yet another tradeoff. By having those two processes, each with three voltage variances and three different sets of gate lengths, you have about 18 different basic libraries and/or memories and each one has a little bit of a sweet spot trading off power and performance.”

Connected to this is guard banding, also called design margin, which concerns how closely you want to go to the edge of the cliff, he said. “Depending upon where people are in their risk profile they will go to various places. If it is a military/aerospace application, they are going to stay far away from the cliff. Likewise if it’s someone making a super scalar processor where there are only going to be 100 of them on the planet, they will go run a bunch of wafers and push it right to the edge and even overdrive the silicon—running it at a voltage above the standard voltage to get it another 15% or 20% faster.”

Staying within the power envelope
At the end of the day, staying within the allotted power envelope is the name of the game.

The system architecture can make a very large difference here, along with running blocks at different frequencies, running them as slowly as possible, shutting everything down when possible, putting the memories to sleep when possible when they are not being used – all of these techniques conserve energy and can make major steps towards having the tightest power envelope.

Brock recommends that engineering teams work closely with their IP vendor at the architectural level when they are selecting their IP. “Don’t wait until the whole thing is designed and say, “Oh oops, I need ‘this’ kind of memory.”