Getting Real About Power Management Verification

How to model analog-like components for power-aware test cases.


By Bhanu Kapoor
SoCs that are used in consumer electronics utilize power management techniques that require control of voltage sources. We have discussed the need for power-aware simulation for verification purposes in the past. EDA tools have advanced to include power-aware simulation such as those found with simulators like VCS from Synopsys. In this article, we discuss the need for modeling analog-like components that must be carried out along with that simulation to accomplish the tasks of writing power-aware test cases.

If we look at the power management techniques such as power gating and voltage scaling and their implications on functional verification, it becomes clear there is a need to model some analog-like components that are present in the SoC environment to enable this verification. A list of typical power management techniques are shown in Figure 1 and have been discussed earlier in the blog articles.


The SoC itself may include multiple cores utilizing dynamic voltage and frequency scaling along with power gating in various modes of operation. The voltage sources can no longer be modeled using 1s and 0s since they take multiple real values during the course of chip operation. Design languages such as SystemVerilog provide “real” data type to model real numbers.

A voltage ramp, provided by a voltage regulator module (VRM), and associated with voltage scaling can be modeled as a triangular waveform. This modeling can include timing information relative of the clock in use. A typical SoC can include multiple scaling sub-systems. The modeling of the scaled clock is similar to that of a voltage-controlled oscillator where output clock frequency depends upon the input voltage.

The models for the level shifters on chip need to be voltage-aware so that voltage-related issues can be captured in their modeling. These need to be connected to the supplies discussed above. The modeling of power switches also need to be voltage and clock aware so that the timing related issues of switching power on and off can be detected in the course of simulation. These are typically one-time tasks and these models can be re-used. And having a clear power management design verification methodology in place is helpful across projects, concurrently and sequentially.

–Bhanu Kapoor is the president of Mimasic, a low-power consultancy.