How Long Will FinFETs Last?

Experts at the table, part two: Tunneling FinFETs; business models; encouraging collaboration.


Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at Cadence; Juan Rey, Sr. Director of Engineering for Calibre R&D at Mentor Graphics; Kelvin Low, Senior Director, Foundry Marketing at Samsung; and Victor Moroz, Synopsys Scientist. What follows are excerpts of that conversation. For part one, click here.

SE: What about tunneling FinFETs as an option beyond FinFETs?

Moroz: Academia has to do it because that’s what industry tells it to do — it’s a try something new, kind of thing. ‘We are not doing it, so why don’t you try.’ The issue with tunneling FETs — I think there are many of them and most of them are a result of the high drivability. IMEC last year presented at IEDM presented a new way — it’s a little bit controversial — you drop the source dopant and the performance improves by 10x because you align the carriers with the tunneling paths, but it works. The bigger issue is variability because if you look at the tunneling FETs without any defects, they are pretty good now. But as soon as you have some trapped system tunneling — and those materials have to be heterojunction III-Vs, and interfaces for III-Vs are really difficult to get right. You always have some traps. Now it is a question of: do you have zero traps, or 1 trap, or 2 traps — the performance changes by an order of magnitude with every trap.

SE: What can be done about that?

Moroz: I don’t think anything can be done.

Low: Whether FinFET can last through 5 or 3nm, according to Moore’s Law nomenclature, I think another function is product time to market. Because of the very, very demanding requirements, at times we have to extend things that are less destructive innovation just to meet the product schedules. In the manufacturing business, there are things that are beyond our control. Customers make the product schedules; we have to find the boundary conditions to work with them and still be able to support the schedules. It may not be ideal because we could do more if given another year, but we don’t have that luxury.

Moroz: Maybe that’s why later on the nature of the evolution of FinFET is just a short fin — but Gate All Around has better gate control — before you go to vertical, which has remarkably better performance, but much more disruptive manufacturing.

Low: And the designers too — the concept of vertical wires …

Moroz: …is a bigger change too. But design is just millions; manufacturing is billions. So design will follow whatever you can make.

Rey: The issue is more, what are going to be the tools to actually do something like this? I have no idea what is going to be the impact on the customer side tools like the digital was — most likely like the digital was, you will be able to isolate everything and keep pretty much the same infrastructure but the customer side tools are very likely going to be very effected — but it will all depend on what will be the architecture of those standard cells. Are they going to be created with these vertical nanowires.

SE: What about when it comes to 3D integration?

Rey: in the case of stacking, while it is way too coarse, even in a technology like that I think we should think mostly as an AND not as an OR — you have quite a bit of impact on the design tools because essentially, you want to go with exploiting what this next technology gives you: a much larger number of vias to interconnect (order of magnitude more for vertical interconnections), among other things — and now you have the resistivity of those vias is so widely different from the ones of the interconnects and that needs to be taken into account with both placement and routing. Even though those things are seen to be mostly in development, not discovering what needs to be done in those tools — not a lot of research — it’s quite a bit of work that is required. I think that the only research activity that is enough information out there is the effort that Leti is putting together called CoolCube. They are talking about 2017 to come up with some demonstration capabilities, but they seem to be saying that you indeed can grow another layer of active silicon on top of an existing one, with minimum perturbation to the devices that are below. They have been reporting only about 10% degradation of those processes.

SE: What seems to happen is that when the techniques are needed, and the customers demand them, they will be developed. Somehow the industry pulls together, and gets the tools developed. Is that model going to be sustainable beyond FinFET when we get to these very interesting ways to either stack or use a new material, etc.?

Moroz: How many semiconductor manufacturers do you expect to be there? How many customers?

SE: Beyond FinFET, who is going to be calling the shots, and will the customer still have clout?

Moroz: If there is one, it might make things easier, actually.

Low: You won’t have a choice. We see the model will continue. The engineering teams and technical teams will always find a solution to bring to bear. It’s how things collaborate that has to continue to evolve. It’s closer now, but is it close enough? Are we reaching out into the system architects from the foundry point of view? Not enough. I think we have to go deeper to understand. The customer also has to be willing to open up. We have seen improvement in that area in things like early test chip development. The first tests may not be successful but they are important for mutual learning. We actually change our PDK design rules according to the learnings we obtain from the customer test chips. Doing one transistor is easy; once we put together millions of transistors — it’s totally different. This learning process has to continue — we don’t see any other way.

SE: How do you get beyond the reluctance?

Gerousis: Mutual customers will drive different parties. If there is a customer, they will drive all parties to work together.

Rey: It’s completely determined by this: very few fabless, huge volume customers that essentially drive the market, because you look at it, there is still a huge diversity of activity on established nodes, and that seems to be growing. But then when you have these very few customers, then this model needs to be tightened: foundry-fabless-IP-EDA, all talking to each other in order to get a solution. The stakes are huge.

Low: The other thing I’ve seen is that the large fabless that get ultimately involved — they are also building more internal capabilities: they are hiring people from equipment manufacturers so they have really deep insight. Likewise, from a foundry angle, we are fortunate because we have our divisions that do design, so we get necessary design rules up front. I think, generally, other foundries are also hiring expertise up into the system level because now we are trying to have a better understanding and predict, before the customer actually asks. It’s not easy but we’ve built some capability for this. In the past, we didn’t have that.

SE: So the fabless companies are bringing people back in that have manufacturing experise?

Gerousis: Yes, and they are looking two nodes ahead, at least.

Low: They speak the same language almost, so we can converse. That is breaking some of the barriers, maybe unknowingly, but it’s happening.

Gerousis: An EDA company never used to interface with [the manufacturing side or the fabless companies], but now we are because we need more collaboration. They need to understand, ‘OK, can we do this in a 5nm regime?’

Moroz: Which means design abstraction is broken?

Gerousis: Yes.

SE: What do you mean?

Moroz: You cannot say, ‘Oh, just do those transistors however you want; I’ll make a circuit of them.’ You need to know exactly how they sneeze.

Rey: We’re talking about all the parasitic accuracy that is required but then there is double patterning that has an impact. The way that you actually need to check even if you have the right protections in different circuits — all of that depends so much on the technology as well as design styles, so that dialogue needs to happen.

Gerousis: At least what they are looking at is an example like doing a fan out with a driver, and the location of where the wire will hit will change the power and performance of that network, at those regimes, especially with bad resistance.

SE: What are the challenges of adding in that level of new understanding into the tools?

Rey: The first part happens mainly because at the lowest level, you need to get a very accurate representation of the circuits. Everything starts with calculating and being able to model both the active and the passive electrical characteristics of each one of the components.

Moroz: Maybe one good example is middle of line. It’s a new concept that came with FinFET. There was no such thing before but now it’s an important effect: there is a new concept, a new design flow.

Rey: Another one would be when, a few years back, people started doing stress engineering, and it was necessary to start measuring more on the actual dimensions of the devices; extract that information such that you can have a much more accurate timing and power estimate of the circuit.

To continue reading part three, click here.

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