Is Asynchronous Technology Ready For Prime Time?

By Ann Steffora Mutschler
As the quest grows to manage power in everything from the handheld smart phone to sensors for automotive applications and contactless payment cards, designers are getting hungry for new design techniques that allow them to hit yield targets within their power budgets.

One such design technique is decidedly not new. In fact, the concept of asynchronous technology has been around for six decades. The first asynchronous processor was used in a system in 1951, but since then it has mostly been relegated to universities and labs. However, asynchronous design approaches are gaining visibility as of late, thanks to a number of low-power benefits the techniques allow and the use of the technologies in commercial applications.

An asynchronous design style differs from a mainstream synchronous approach in that no clocks are used. The chip is not governed by a clock circuit or global clock signal, but instead waits for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. By contrast, circuits designed with a synchronous approach operate according to clock-timing signals.

One of the issues with synchronous circuits is that if there is no data, the circuit is still being clocked constantly. That produces power dissipation, which is not ideal, noted Gary Lee, director of product marketing at Fulcrum Microsystems, which uses asynchronous technology to design its 10GbE switch chips.

“Asynchronous technology is basically clockless, and has two states of logic. One is a pre-charge state where everything is charged to a logic high; and then there is an evaluation phase where the logic is evaluated and if it evaluates to a certain condition it may pull that state lower,” he explained.

Lee pointed out that there are various ways of creating asynchronous logic, one of which is a handshaking technique such that, “things get evaluated and when they are finished being evaluated the results are ready for the next stage. The next stage can then start doing its evaluation. It’s not timed to a clock, so it eliminates things like race conditions and other things you might see in standard synchronous logic. It also allows higher performance in many cases so you can evaluate things more quickly as they ripple down the chain of events that get evaluated.”

Specific to low-power applications, if there is nothing to be evaluated, the logic is basically sitting idle until it’s needed and is not going to draw power. Even though CMOS has leakage current, as far as clocked power it’s not going to see it unless it needs to evaluate something, Lee said. “In our chips, power dissipation is based on a level of activity. In our 10GbE switch chips, if you are sending a lot of data into the ports, the power will be higher. If you are at a period where there is no data being transmitted for a period of time, the power will be very low–it just depends on the level of activity.”

Another fabless semiconductor company that has leveraged the benefits of asynchronous technology is Octasic, which is focused on high-density DSPs. While you may not think ‘low-power’ when it comes to DSPs, VP and CTO Doug Morrissey pointed out that even though there are no batteries for the applications its chips go into, devices are plugged into the wall and all of the focus is on performance. Given the density of components in advanced manufacturing technologies, power becomes a limiting factor as to what can be packed in. It is also a huge cost driver of the overall platform cost, he said.

Octasic finds the benefits asynchronous technology to have somewhat of a multiplicative effect. “We find that in our particular approach to asynchronous, and we are particularly focused on processors, we’re able to basically shrink the whole design, eliminating a lot of states and lowering capacitance. That shrinks drivers, which in turn allows much smaller overall power characteristics and eliminates large synchronous clocks. At the high end, clock distribution alone can chew up 30 to 40% of the power in a high performance DSP. In a competitive embedded world, that had better be down around 10% because by increasing design complexity you are able to do tons of clock gating. But the clock gate from a design management standpoint and again from an area clock standpoint just makes it that much more difficult,” Morrissey noted.

Asynchronous techniques lack tools
With all of its benefits, it seems a mystery as to why this design style has not caught on in the mainstream. One good reason is the lack of easy-to-use design tools that can be integrated into traditional, synchronous tool flows.

Both Fulcrum and Octasic use a combination of commercial, off-the-shelf EDA tools, and internally developed tools along with work with universities such as USC.

In Fulcrum’s case, its chips are a combination of synchronous and asynchronous technologies, and Lee noted that its designers use off-the-shelf, standard tools for all the synchronous logic. From the asynchronous point of view the tricks are the cell layouts themselves, the various building block layouts and the compiler is a key one to develop something that you can go from RTL to logic or a construct of asynchronous cells.

To address this dearth of asynchronous design tools, French start-up Tiempo, which delivers its technology in the form of synthesizable IP cores and synthesis tools, is setting out to change things. Serge Maginot, Tiempo’s CEO, said company’s technology is used for the design of asynchronous and delay-insensitive ICs—delay insensitive meaning that it is functionally correct regardless of any delay in gates and wires and that it has no delay assumption. All of this is meant to allow designs with both ultra-low-power and high-performance, and can be described with higher-level models in standard language.

“I do believe 10 years ago the motivation of designers to change their habit from a synchronous methodology to an asynchronous methodology was not so strong because they always could find an easy way to improve the performance—in terms of power consumption—using standard synchronous methodology. You still find customers today that believe they can improve a process doing simple changes on their design, but I really see that more and more designers and design managers are starting to be convinced that it’s time now for a change in design methodology because they see the limits of the current approach,” Maginot observed.

Another interesting point to note that could tip the scales in convincing designers to at least try out the technology is that Tiempo’s asynchronous IP cores can be added next to synchronous blocks in a chip through the use of interfaces.

“Every asynchronous IP we have can be delivered with, at the top level, an asynchronous-to-synchronous interface that is generated by the tool, so we can really plug one asynchronous block (either a generic IP or a custom block) into a synchronous environment,” he explained. “We never try to convince customers to switch 100% from synchronous to asynchronous documentation. There is a path to adopting the technology in an incremental manner.”

In addition to a general lack of tools limiting the exposure of asynchronous design, these techniques have not been traditionally taught in university logic design and circuit design courses but Lee, Maginot and Morrissey believe that could change in the not-too-distant future as asynchronous design styles are used even more in commercial applications, and as more tools come on the market.