Is Your Voltage Drop Flow Obsolete?

Voltage drop at advanced nodes is a deadly serious problem that has become unmanageable with the methodologies used by most chip designers today. This article will cover the reasons why power integrity has risen to a top-of-mind concern and why it has become almost impossible for today’s EDA tools to measure and fix it. We will then look at some radical methodology rethinking that is needed to regain control of power integrity signoff, and how this will impact all advanced node design flows going forward.

There are a couple of reasons why voltage drop has gotten so much bigger at advanced nodes. The first reason is that new finFET and gate-all-around (GAA) transistor topologies manage to cram a lot of transistor channels into a very small area. This raises the current (I) density. And the power supply current flows through wires that are ever smaller with higher resistances (R). A simple glance at Ohm’s Law, V = IR, explains why rising currents and rising resistances cause voltage drop to become worryingly large. So, delta-V is now bigger in absolute terms.

The second reason is that power and heat dissipation have become a huge problem. The #1 most effective technique for lowering total power is to lower the supply voltage. That’s because CMOS switching power is proportional to the square of the supply voltage (P = CV²f). This means that the incentive is to lower the supply voltage (V) to the absolute minimum possible, especially for high-performance designs with high operating frequencies (f). But that leaves only razor thin margins for any voltage drop in the power distribution network (PDN). That means voltage drop now needs to be managed extremely carefully.

The real-world symptoms of these challenges are that multiple advanced node customers have reported a drop of about 10% in maximum achievable operating frequency (F_max). They found the root-cause to be IR drop ‘escapes’: unanticipated and unverified switching scenarios that cause a higher-than-expected voltage drop. Other design groups see the exact opposite, with silicon F_max performing well above design specs. This means they have overdesigned and are using more power than needed. Either way, this is leading to a persistent gap between what the signoff tools predict and what the silicon actually delivers. Power integrity signoff teams are responding by investing huge amounts of time and compute resources as they try to catch more issues before tapeout or optimize their design characteristics.

Now that we have looked at why voltage drop has become so important, we need to answer the question of why it is so difficult for today’s EDA tools and methodologies to predict it. What has changed, beyond IR drop just getting higher? The key insight is that dynamic voltage drop has become absolutely dominant in determining the worst IR-drop scenarios. It is important to understand the difference between static voltage drop and dynamic voltage drop (DVD): Static voltage drop analysis assigns average switching activities to standard cells and models them as constant current sinks. This is useful for evaluating a power distribution network early on or to evaluate the overall architecture of a PDN. The assumption is that the PDN will be able to quickly supply any individual switching cell with the current it needs, independently of what neighboring cells may be doing.

Unfortunately, that assumption no longer holds. The intense, short bursts of current drawn by advanced node cells are difficult to satisfy through long, thin supply wires that must carry current from electrically distant power pads. And if multiple cells in the same area all switch at the same time, then the local voltage will dip significantly as the PDN struggles to deliver the necessary current through large parasitic resistances. This local voltage drop effect is exactly similar to your lights dimming when the air conditioner switches on. Dynamic voltage drop is now much more significant and completely dominates static and self-drop in the local context.

Now we come to the crux of the voltage drop problem for EDA: In order to calculate the worst-case voltage drop we need to identify the realistic worst-case combination of simultaneously switching cells. But that search space is so vast that it is impossible to check all possibilities. It’s easy to see that N cells have 2^N possible switching combinations, and N is typically in the millions. Clearly, not all switching scenarios are relevant (e.g.: cells that are very far apart) or even possible (e.g.: logical correlations and timing window overlaps restrict the possibilities). Despite these filters, there still remain an uncountably vast number of realistic switching scenarios. The drops in F_max in silicon that we discussed earlier are typically due to real switching cases that cause significant local voltage drop but were missed by the signoff methodology. This is called the “coverage” problem.

The voltage seen by the victim cell at the center of this IC placement region is affected by the switching of its neighbors. The strength of the voltage coupling between the victim and each aggressor is displayed as a heat map in this SigmaDVD analysis for that victim.

Current DVD coverage methodologies rely on providing a large set of activity vectors and asking the power integrity tool to perform a transient analysis for each vector (a ‘vector’ is essentially a list of cells switching in the same clock cycle). These vectors typically come from simulations that, ideally, capture real circuit behavior. These are often complemented with vectorless analysis. “Vectorless” is a confusing misnomer and is identical to vectored analysis except that the activity vectors are generated automatically by the EDA tool (think ATPG). So, to the user it looks “vectorless” but, under the hood, it still relies on design activity.

While vectors are certainly useful to validate a set of known activity scenarios, they don’t provide good voltage drop coverage. Estimates put vector coverage in today’s flows at less than 10% of realistic switching scenarios. The answer might seem to just provide more vectors but that is not feasible because (a.) transient analysis for each vector is highly compute intensive which limits how many vectors can be analyzed in a realistic time, and (b.) even with many more vectors, the coverage would still remain low because the search space is so huge.

There is another issue with vectored DVD analysis that is not commonly appreciated. A transient analysis of a specific vector is numerically unstable and is very sensitive to the exact input conditions, simulation time step, and other details. Even tiny shifts in the timing window boundaries have very large effects on the resulting delta-V. This makes the coverage problem even worse and lowers the reliability/reproducibility of the current approaches.

And that is where the industry is today – Despite investing huge amounts of compute resources to analyze power integrity, advanced node designers are left with low DVD coverage and still facing silicon escapes. Ansys is the industry leader in power integrity signoff and has invested very considerable engineering resources over the past few years into solving this problem. They have developed a radical new approach to DVD based on a technology called SigmaDVD. It is a significant engineering breakthrough that rethinks the entire DVD issue from the ground up. SigmaDVD technology is part of Ansys’ RedHawk-SC power integrity signoff tool and SigmaDVD is now in production use at multiple leading silicon vendors. This follows several years of collaboration to validate not only the technology itself but also the new methodology it embodies.

The concept of SigmaDVD is to achieve very high DVD coverage by moving away from reliance on vectors. This shift is very similar in concept to the way static timing analysis (STA) replaced circuit simulation (SPICE) for circuit timing signoff. Just like STA, SigmaDVD does not rely on activity vectors to analyze a circuit and, just like STA, it provides very high level of coverage in a short time with just a fraction of the transient analysis effort. Yet, its results are still rooted in fully accurate transient analysis and the results can be verified in SPICE.

The basic approach of SigmaDVD is to pick each cell in the design in turn and do a single transient DVD analysis of the entire circuit for each victim cell. Based on these results, SigmaDVD is able to accurately predict the voltage drop of any combination of aggressors and victim. This radically new analytical technique, combined with the power of the Seascape elastic compute platform, is linearly scalable with design size and offers benefits that are numerous and far-reaching:

• Firstly, this approach is hugely more efficient than doing transient DVD simulations for every single vector. It is a much faster analysis requiring a fraction of the compute resources.
• The DVD analysis is vector independent! Just like STA
• The very fast calculation enables orders-of-magnitude more coverage of realistic switching scenarios, including user-generated vectors
• SigmaDVD analysis early in the design flow can quickly generate P&R directives that avoid voltage drop violations or reduce maximum delta-V without impacting design performance. This can have a huge impact on designer productivity. One customer reported that about 25% of his team’s bandwidth in RTL2GDS flow went into fixing IR violations. They are looking to SigmaDVD to eliminate a lot of this effort.
• The voltage drop contribution from each aggressor is quantified and allows SigmaDVD to report a ranked list of the top aggressors for every victim cell. This gives designers root-causes and specific fixing targets, which is crucial for effective avoidance and debugging of DVD violations
• The reverse is also true: You can rank the top victims of any selected aggressor cell
• The voltage impact on any victim cell can be calculated independently from the others, allowing linearly scalable parallel processing
• SigmaDVD results are numerically very stable. Small changes in the circuit setup will cause only small shifts in the result
• SigmaDVD results are provable in SPICE (see IDEAS Digital User Forum on Nov 30^th for a customer paper that does a deep dive on this point)

The advantages of SigmaDVD technology are useful early in the design process for shift-left avoidance of DVD issues, and also during IR-ECO debugging at late-stage closure with precise root-cause analysis to guide fixing for signoff closure.

Example of a specific switching scenario analyzed by Ansys RedHawk-SC using SigmaDVD technology. The simultaneously switching cells are highlighted in colors that correspond to their degree of impact on the victim cell in the center

SigmaDVD is a powerful additional new technology that addresses the most urgent and difficult problem in power integrity signoff for advanced nodes. It provides much more comprehensive DVD coverage in less time and identifies root-causes with efficient shift-left techniques to avoid and fix voltage drop violations. Deploying SigmaDVD requires a methodology shift for chip designers and changes their existing signoff flows. Ansys does not underestimate these challenges and has been collaborating closely for several years with leading customers to mature and prove out the technology and deploy it on real production designs. Ansys believes this new SigmaDVD approach will become the standard methodology for DVD analysis in advanced node design flows. To learn more, please register for the panel discussion with Qualcomm and Microsoft at IDEAS Digital User Forum on “How Leading Customers are Radically Rethinking Power Integrity Analysis and Breaking Through the Status Quo”