It’s Late Q3 – Do You Know Where Your Chip Is?

By Mike Gianfagna
Design complexity is increasing. We all get that. But there are other forces at play that may be more significant. Supply chain complexity is also increasing. Outsourcing and off-shoring continue to rise. There exists a general tendency to surrender the fate of your chip to more people. Overlay this situation with the simple fact that in more and more cases the chip defines the product. The fate of many new products hinges on the ultimate goal of a successful, right-first-time implementation of the product’s SoC. And that chip has a lot of hands on it, making it harder and harder to figure out if the ultimate goal can be reached. Who gets involved?

Third party IP suppliers to start with. More than 70% of most SoCs today are composed of re-used third party IP. Then the design team takes the ball. At the very least, this group is located in a few places around the world and parts of the design could easily be outsourced to teams with specialized skills. Let’s not forget the EDA tool chain, which has a fundamental impact on the quality of the design. This tool chain is constructed of software from multiple vendors, which everyone hopes will interoperate flawlessly.

When it’s time for tapeout, the foundry gets the ball. And then assembly and test operations. Did I mention that the substrate, package and test hardware come from other vendors as well? You get the picture. For this long, complex, multi-national supply chain to work perfectly and deliver the desperately needed working chip on time might be considered a miracle. Sounds like the whole process could benefit from some kind of logistics management and coordination, right? Maybe an integrated, Internet-enabled information backbone that tracks all this in real time.

There indeed are systems that aim to fill this need. Product Lifecycle Management (PLM) tools are supplied by many large enterprise software companies such as Dassault Systemes, Oracle, PTC, SAP and Siemens. If you search Wikipedia, you’ll find a nice holistic diagram of what PLM software manages.

Look carefully around the 10:00 mark on this chart. You will find “EDA” and “CAE” there. This is a pretty small piece of the process, yet for many products these processes have the largest and most profound impact on a product’s success. OK, I’m an EDA and semiconductor guy and perhaps I have a biased point of view. If you look at some of the most successful consumer products of our time, I don’t think so however.

So, what do PLM vendors do to monitor and manage those two little areas on the above chart? I’ve looked at a few reports from various PLM vendors. You will find statistics about the SoC portion of the project – the data source is often labeled: “extracted from operations review slides.” That information source can be out of date and can also suffer from subjective bias. If you work in the EDA community, you should start smiling right about now. What do a lot of our products do on a daily basis? We analyze the quality of the chip, enumerate the errors found and help to repair those errors with the ultimate goal of delivering a working chip on time. Many EDA tools generate up-to-date, objective and accurate information about the state of the design. Software that performs these functions is found throughout the far-flung supply chain that is working on that precious chip.

What if this information source could be merged with a PLM data backbone? Could information accuracy and decision support be substantially enhanced? I think so. This line of reasoning suggests there is an opportunity for collaboration between EDA and PLM vendors – a collaboration that could potentially open up new markets and new applications for EDA. Is this a win/win/win (customer/PLM vendor/EDA vendor)? Could be. Will end product developers pay for a transparent, accurate picture of the status of the SoC they so desperately need? They should. Time will tell if they will.