Leakage Optimization

By Arvind Narayanan
For consumer electronics such as cell phones, tablets, and laptops, long battery life is a key requirement. Battery life is directly related to total power consumption—which is a function of switching activity, capacitance, and voltage—across all operational modes. In full active mode on a cell phone, for example, the dynamic power that comes from signal switching is high; in standby or sleep modes, the battery still drains because power leaks from inactive transistors. Also worth noting is that as we move to smaller technology nodes, the leakage power component is becoming the dominant factor. As a result, mobile devices are tethered to the wall plug more often than we prefer. So, reducing leakage power should be a primary goal for any power-conscious chip designer.

Leakage power (or static power) is a function of the supply voltage (Vdd), the switching threshold (Vt), and transistor sizes. Therefore, you can reduce leakage power by lowering the Vdd and by using multiple voltage threshold (multi-Vt) standard cells. These are accomplished at the architectural level by using multiple voltage islands (domains), and through cell-level optimization. Leakage optimization can be an enormously complex problem when you consider the explosion in the number of corner, mode, and power state scenarios that could have conflicting power, timing, SI, manufacturability, and area closure requirements. Additionally, the worst-case power corners don’t necessarily correspond to the worst-case timing, so it’s virtually impossible to pick a set of corners that will result in optimization across all design objectives without excessive design margins. Running separate optimizations on various scenarios requires multiple RC extractions, timing analysis runs, and power analysis runs, which increase the engineering effort during the final stages of the chip implementation. This leads to unpredictability in signoff ECO loops because the results don’t converge, and also impact design performance, power consumption, and area.

The optimization engine should be able to holistically address all the possible scenarios concurrently and make intelligent tradeoffs between power, timing, and area also referred to as multi-corner, multi-mode (MCMM) analysis and optimization. MCMM should not simply combine views, or force the designer to choose a subset of possible mode/corner/voltage combinations and add margins to hopefully cover the rest (Figure 1).

MCMM optimization includes replacing low-voltage threshold (Vt) cells with high Vt cells, to reduce leakage power. High Vt cells can increase delay, so it is crucial to have an accurate MCMM timing engine determining which paths can tolerate high-Vt cells and still meet timing under all corner-mode scenarios.

For any given complex design that has multiple modes, corners, and power states, you can realize significant savings in leakage power by using a true and concurrent MCMM optimization solution. Users of your mobile SoCs definitely will appreciate a little more freedom from the power plug.

Figure 1. MCMM power optimization concurrently optimizes timing and power across all power states, operational modes, and process corners.

—Arvind Narayanan is the Olympus-SoC product marketing manager for Mentor Graphics’ place and route group.