An LLE-aware design flow that increases design operating frequency while reducing power.
As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches.
This paper describes a LLE-aware design methodology that mitigates the conservatism of conventional cell characterization. This methodology detects physically placed neighboring cells near the target cell, translates the target cell’s LLE physical parameters into electrical parameters (Vth/u0), and selects the corresponding delta LLE timing/leakage cell from an augmented library.
This methodology was deployed for a 3nm production tape-out with clear power, performance, and area (PPA) benefits achieved.
Read more here.
Fig.1: Flow for LLE-aware layout. Source: Synopsys.
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