Low Power Simulation

By Luke Lang
Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP structural verification. But if it will help you sleep better at night, then go for it.” For the longer answer, keep reading.

In order to run VDD/VSS-aware simulation, one must have VDD/VSS-aware simulation models. This is not commonly available for all libraries and may need to be constructed. Construction and verification of a simulation library is not an easy task. It must be planned well in advance.

With VDD/VSS-aware simulation models, the outputs of the library cells will be corrupted (forced to X) when VDD and VSS pins are not at the ON state. These power pins are driven either by the testbench or by power switches through the power net connections. The main idea is that if the power nets are incorrectly connected, then the library cells will behave incorrectly and result in a simulation failure.

That sounds fine in theory, but in practice, gate-level simulation is difficult to bring up and runs much slower than RTL simulation. VDD/VSS-aware simulation will run even slower because VDD and VSS pins need to be evaluated for every gate at every simulator event. Also, those that do run gate-level simulation will only run a very small subset of the overall tests. This leads to question about coverage. Are these few tests adequate for verifying power and ground net connection?

When compared against power-intent-based LP simulation, VDD/VSS-aware simulation behaves almost the same. The shutoff control signal either directs the simulator to perform the state corruption or turns off the power switches, which leads to the simulation model performing the state corruption. In the latter case, the power and ground nets do play a role in transmitting the shutoff control to the VDD/VSS-aware simulation models. However, power and ground connection is inherently a structural issue. It can be verified much more efficiently and completely by a LP structural verification tool.

For example, gate A should be always on but is connected to a switchable power net. When the power net is switched off, gate A drives an X at the output. If the next gate, B, blocks this X, then this power connection error cannot be observed. This is the well-known problem with pattern-dependent nature of simulation. Using LP structural verification, gate A can be shut off and drives always-on gate B without going through an isolation cell. This is immediately flagged independently of any simulation patterns.

The bottom line is that LP structural verification is an absolute must. VDD/VSS-aware simulation is optional. You could try it in an attempt to sleep better at night. But be sure that attempt doesn’t keep you working all night long. It may not be worth it.

–Luke Lang is a senior product engineering manager at Cadence.