Low-Power Solutions At DAC

Despite concerns about power, automating the analysis and implementation remain a problem.

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By Bhanu Kapoor
Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low power design.

Analysis, verification, and implementation are the three key areas for power related tools. Let’s take a look at how we have progressed over the years in each of these segments of low power design.

Power Analysis
Power analysis tools for RTL and gate-level have been around for a while. At gate level with parasitics extracted from the backend, you can get power estimates that are trustworthy and Synopsys’ power analysis solution, now part of PrimeTime PX, can be regarded as the gold standard here. Vector-dependence (for both dynamic and leakage power) becomes an issue due to the slow speed of gate-level simulation. There hasn’t been much innovation at RT-level over the years even though several vendors now provide RTL power analysis. System-level power analysis is considered good if it can predict the direction of change and order of magnitude well, but none of the solutions are mature yet. Software power estimation is still being done based on average power data for instructions, which can vary significantly depending upon data being fed to the instruction.

Power Management Verification
This is an area that has seen progress over the years with several tools for rule-based, simulation-based, and formal checking of issues due to voltage-based power management techniques used on typical low power designs today. Atrenta, Cadence, and Synopsys have solutions for rule-based checking. Synopsys, Mentor, and Cadence provide solutions for power-aware simulation by extending their simulators to read power architecture description written in formats such as specified by IEEE p1801. This helps introduce appropriate power effects appropriate for a power state of a device that uses power management techniques such as power gating with state retention and voltage scaling. Synopsys has also extended its equivalence-checking tool (Formality) to be power-aware in validating equivalence of descriptions that may include power-related changes. Power related assertions can be verified using regular assertion checkers.

Low-Power Implementation
The key power reduction tools still are those that help with the insertion of gated clocks and MTCMOS cells. While typical techniques used for power management today include power gating, power gating with retention, voltage scaling, and adaptive body bias, we don’t have EDA tools that take a design description and automatically modify the design for use of these techniques leading to a lower power implementation. The use of these techniques requires knowledge of the design specification, and there lies much of the problem in automation.

–Bhanu Kapoor is the president of Mimasic, a low-power consultancy.