Market Catches Up With Verification IP

By Ed Sperling
Ever since verification IP was introduced it was seen as something that should be given away with purchased IP. The result was limited investment by IP vendors, frustration on the part of IP customers, and a market opportunity that nearly fizzled before it even began.

But as the amount of commercially developed IP content continues to grow in ICs, the potential interactions increase with neighboring IP blocks and tools, and time to market pressures continue to mount, the market for verification IP also is growing. The proof is in the amount of investment now being poured into this technology by the large IP vendors—most notably Synopsys, Cadence, Mentor Graphics and ARM.

“VIP is the hottest growth segment in verification,” said Michael Sanie, director of verification product marketing at Synopsys. “But after 10 years of patch over patch we’re starting to see multiple problems. One is performance. Three million lines of code is average for an SoC. The second is debug. You use VIP for that, but it’s still hard to find the bugs. And the third is that it takes up to four weeks to set up and integrate within a verification environment.”

The reality is that verification IP will never actually reduce the time spent in verification, which can run as high as 75% of the total NRE for an SoC. But done right, it can improve time to market and make chip companies more confident about stopping verification, which is always a judgment call.

Make, buy, or make do
Most of the commercially available has at least some verification IP bundled with it. That VIP is there to prove the IP works. But there’s a whole other level of VIP under development now that’s sold separately.

“If you get VIP with the IP, it’s very targeted or constrained,” said Jason Polychronopoulos, product manager for verification IP at Mentor Graphics. “To do the job properly, verification IP should reduce the verification effort. There are a few things you need to do that. One is that it needs to fit into the verification flow, which increasingly involves UVM. The second is that it needs to be complete. This is not just a question of driving a stimulus. It needs to do complete protocol checking and coverage. The third is that it needs to be part of an overall verification plan, which is executable and linked to results.”

The last part is where all three of the big EDA players see opportunity. Complexity in design is bad enough. But trying to add it into an existing automation flow is particularly difficult. And while many design flows are still a mix of proprietary and commercial tools, verification is weighted heavily toward the commercial side. As more third-party IP gets incorporated into designs, being able to verify it in the context of what interacts with that IP, as well as the context of how to test it all from a block, subsystem and even system level will become more critical. And while most companies were well aware of what was inside their own IP, most commercial IP is viewed as a black box. Taking the time to understand all of its intricate behavior is a luxury most design teams don’t have.

So while some chip developers may opt for the free VIP, the more commercial IP that is used the less sufficient those tools will become—even at mainstream process nodes. But that doesn’t mean there won’t be a lot of grumbling from the customer base.

“The whole problem is getting harder and harder,” said Simon Butler, CEO of Methodics. “At some point the consumers of IP will have to ante up. But there also will be a lot of pushback. They assume that if they buy IP it should just work, and companies are always on the verge of thinking, ‘Why not just develop the VIP ourselves?’ But there are so many problems and so many versions of IP they never do. Still, you’re going to hear questions about the value.”

He noted that ARM cores come with a verification suite to make sure no bugs are introduced and that timing remains intact. But when other things are jammed around that core problems can creep in. “In theory, this should all be plug and play. But the reality is you can’t come up with every corner case.”

Abstracting up and down
Another twist in current VIP usage is that it has to work with transaction-level models created with the TLM 2.0 standard, and it still has to link back down to problems that surface at the register transfer or gate levels.

“The VIP that’s out there today is based on Vera or e or C,” said Synopsys’ Sanie. “Over time it will need to be configured to work with VMM, OVM and UVM.”

This is no simple task, though. Sanie said the VIP for USB 3.0, for example, now is about 500,000 lines of code. There is an estimated 30 million lines of code in RTL and testbenches on an SoC. In comparison, Windows is only about 50 million lines of code.

But that’s also code that a company doesn’t have to generate itself. Just digesting the amount of information in standard interfaces such as PCI Express 3.0 involves thousands of pages of information. A smart phone may have 20 of those types of interfaces.

“Nobody can do more than one or two,” said Tom Hackett, senior product marketing manager at Cadence. “You must import expertise into the project. When you’re the IP creator the view is that you want to get the IP out the door and you limit what’s good enough for verification. On the verification side it’s different. You want to exhaustively test the IP. You want to verify the IP block you’re implementing works. But you also want to put it in the context of the rest of the chip. And then you need to integrate it with hardware and software and across the whole development flow. VIP has to play a role across the spectrum.”

He noted that if you’re generating the VIP yourself, you’re only learning from your own company’s past projects. VIP that is commercially developed incorporates knowledge from multiple customers.

Competitive advantage within
Not everyone wants to sell this kind of technology. eSilicon, for one, believes there is a competitive advantage in knowing what works best where and in being able to verify it internally for customers.

“We’ve invested quite heavily in these kinds of utilities and in capabilities to evaluate different IP,” said Jack Harding, eSilicon’s president and CEO. “This is comparable to how place and route tools progressed in the 1990s. At first, they were there to augment the smart engineer. Once it was automated, the engineers could oversee the process. IP is heading down a similar path for power, performance and area. We need to produce analytics that are the equivalent of place and route and run permutations of voltage versus temperature versus performance. The human brain can no longer process this many variations—and make sure it still works.”