Memory VIP

As the consumer market, and the mobile segment in particular, continues to demand more features and more performance in their gadgets, the designer community is confronted with myriad challenges of delivering on those demands – not the least of which is verifying compliance of ever-evolving protocols that enable the connection of everything within the system on chip (SoC), and the connection of the SoC to the outside world. Protocols must continually evolve to deliver higher bandwidth and more features while maintaining lower power consumption for longer battery life. Some of the recent protocol changes include the release of M-PCIe, the addition of a new C-PHY to MIPI protocols, increased speed for MIPI D-PHY, and of course the release of LP-DDR3 and LP-DDR4. All of the components on an SoC need to be verified for their compliance to their respective protocols so that the SoC can be rapidly assembled around the major system architecture and can communicate with memory and external devices such as displays, cameras and sensors. A typical mobile SoC will include protocols like AMBA AXI4, USB, HDMI, eMMC, MIPI CSI-2, MIPI DSI, MIPI BIF, LP-DDR3/4, I2C, I2S and so on. Designers need an intelligent and broad selection of verification IP to quickly validate the major architecture decisions based on the market requirements. To understand the importance of having the right VIP, consider the verification of a critical part of the SoC, the memory interfaces. Memory VIP can be used in three ways:

• To verify that the memory controller complies with the JEDEC standards. Hence that it supports almost all the memory vendors’ parts;
• To quickly integrate a specific vendor memory part number into the SoC testbench with confidence that the memory will behave as expected, and
• To drive representative traffic through the SoC to enable SoC verification and power analysis.

It is advantageous to have a Memory VIP that provides all of these capabilities within a Universal Verification Methodology (UVM) environment that enables randomization of configurations without having to instantiate different memory models or recompile (Figure 1).

Fig 1: SystemVerilog architecture including advanced features for configuration and debug.

For memory controllers, VIP is primarily used to verify that the controller complies with two standards, the on-chip bus such as ARM AMBA AXI, and the external memory interface such as JEDEC LPDDR4 and LPDDR3. The SoC bus VIP will initiate transactions, and the memory VIP acts as the memory array and delivers memory data to the controller on request with the goal of testing compliance and ensuring that the controller meets the timing requirements for a particular part. Typically, the memory VIP would be preconfigured with data to save on simulation bring-up time. The memory VIP delivers protocol compliant transactions, injects errors and skew to verify correct error handling by the controller, checks for any non-compliant behavior from the controller and provides coverage of the protocol. Also, it offers a pre-defined verification plan derived from the JEDEC specification. While the VIP is modeling behavior of the protocol, the controller is in RTL and can be analyzed for power efficiency during specific aspects of behavior. Debug information and easy browsing of memory contents (Figure 2) at any point in time help to quickly find the root cause of any memory problems.

Fig 2: Debug information and easy browsing of memory contents help to quickly find the root cause of any memory problems.

Once the controller is verified and targeted for a specific design, the designers will typically want to verify against the specific components being used in the end product. This is where randomization becomes very important. Memory VIP can be configured to act like a specific part number. Changing the memory density, the number of data bits, timing, and the protocol characteristics, should all be achievable without the need to instantiate different components, which is typically the case with vendor-provided models. The power and performance demands of the consumer market will continue to increase, driving continued advances and evolution of SoC-based protocols with memory interfaces at the forefront to provide low power and performance. By arming themselves with the right VIP, aligned with constrained-random verification of UVM environments and advanced features, designers will be well-equipped to meet those demands. For more information on Synopsys’ portfolio of SystemVerilog-based memory, interface and bus VIP click here. To access a recent webinar entitled “The 10 things to know about memory verification: Introducing Synopsys Memory VIP,” click here.