Mind The Gap

The growing divide between high-level tools and RTL tools is creating inefficiencies and adding to the cost, but it’s not all bad news.


By Ed Sperling
Throughout system-level design there are gaps. High-level modeling doesn’t connect directly to RTL code. Synthesis and high-level synthesis remain worlds apart. There are even gaps in the expertise, from the people who handcraft RTL to those who take it for granted.

Some of these gaps will get closed over time. Others will never be closed. In same cases it doesn’t matter. In other, it adds inefficiency into the flow. Gaps can result in errors, they can delay designs, and they can cost money.

“There is always a gap between those two stages,” said Serge Leef, vice president of new ventures and general manager of Mentor Graphics’ System-Level Engineering Division. “There is no implementation path from ESL onward. In fact, the two worlds are barely connected. People who do system-level modeling are basically done because the benefits of that system model are not connected to implementation. Test benches become the ‘bridges’ between the two worlds.”


Leef said that what is missing is true system synthesis. Right now engineers work with synthesized blocks or even pieces of blocks, but it takes far too long and too many cycles to synthesize an entire SoC.

“There are too many dimensions to optimization,” he said. “Add software and the number of optimization knobs is vast. Also, there’s no really good language for synthesis that addresses concurrency, timing and pre-emption. SystemC, which is the best we’ve got, is really a hardware modeling language. On the software side there are C and C++, and lately there’s been a push toward UML and SysML. But there is no single language that does everything.”

System prototyping
Industry consultant Gary Smith said the one critical piece that has been missing in ESL-based design is virtual prototyping.

“That’s the only way we’re going to be able to fix the flow and get the cost of the design down and get simulation,” said Smith. “We need RTL handoff.”

One of the key pieces in this puzzle is software prototyping. Both Intel and Synopsys have been on an acquisition spree in this part of the market lately, grabbing most of the startups. Smith said the prototyping has to be radically faster, though, for it to have a real impact on design—something in the neighborhood of 100MHz.

The second missing piece is virtual prototyping for hardware. Both Atrenta and Cadence are known to be working on this problem, and sources say all the major players are exploring this market.

But Aart de Geus, Synopsys chairman and CEO, said all the pieces may never come together. “There will always be different levels of abstraction,” de Geus said. “The benefit of one level is not the same as another level, and you need success on all levels of abstraction. There will always be a tradeoff between efficiency and quality of design.”

He noted that there is a big difference between systemic complexity and the scale complexity inherent in Moore’s Law. “The opportunity is to keep scale complexity going while dealing with systemic complexity.”

Alex Shubat, president and CEO of Virage Logic, said the future may be in integrating the supply chain rather than the individual pieces of technology.

“Everyone has a center of excellence,” Shubat said. “The key is to make sure you can integrate up and down. No one company spans the whole world. The bigger the vertical stacks, the greater the efficiency. If it all works smoothly, you should be able to get to tapeout in half the time.”

Unexpected winners
That has paid off for IP vendors, who provide some of the pieces. It has created new opportunities in other areas. For example, the disconnect between the high-level modeling tools and the engineers who like to see exactly what is going into synthesis has opened the market for tools that can dig down into the code and analyze it. Mike Gianfagna, Atrenta’s vice president of marketing, said his company discovered that somewhat accidentally when chip developers began using Atrenta’s SpyGlass exactly for that purpose. It was an unexpected win for the company, considering SpyGlass was created to analyze RTL.

“There are a completely different set of things that each of these groups care about,” said Gianfagna. “With high-level synthesis you get machine-generated RTL, but you generally don’t know what the machine generated. Then you’ve got the other side of the engineering world where they handcraft RTL. They want to know what’s in the RTL, but the machine-generated RTL from high-level synthesis is not all that well documented.”

The result is that not everything can be optimized effectively without that level of granularity. But at the same time that higher level of abstraction is essential just to get the analysis done. Every time a team of engineers wants to do synthesis place and route it can take the better part of a week. Both speed and automation are essential, but it has to be linked back to the RTL side.

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