Money And Power

By Barry Pangrle

Companies developing products work within the realms of cost, features and quality. As the old saying goes, “choose two.”

For chip design teams, the budget for the production cost of the chip is usually a constraint that is handed to them. Often that budget is not just the cost of the silicon but the cost for a finished part that is tested and packaged and ready to be placed onto a board.

It was while I was working on a chip design team about a decade ago that I caught my first glimpse of what was waiting down the road in terms of power issues for design teams. We were designing a part with nearly 2 million place-able instances and a half meg of on-chip SRAM. It was a fairly good-sized chip for those days. With a quarter million flops and almost all of them being driven by the same clock, we had some concerns about IR drop. The solution was to go to a flip-chip package and remove the limitation of only being able to bring in power from the periphery of the chip.

Based on our power estimates, we were looking at a ceramic package in order to handle the heat. After calculating the yield based on the fab’s defect densities and determining that initial yields wouldn’t be that great, the next rude surprise was that we were going to be paying a lot more for the package than we were for the silicon. Even at relatively low yields we were confident that could be greatly improved; the silicon was still significantly less expensive than the package. Chip area? Yield? We still cared, but it was clear that the path to a lower cost part was going to be through getting into a cheaper package and that meant reducing the power.

One way to reduce the power of a design is to reduce its functionality. It stands to reason that if there’s less functionality on the chip that there’s going to be a reduced need for power to drive it. On the flip side, if I’m clever about how I’m using energy in my design, I might just be able to squeeze some additional features onto the chip and still meet my power budget and get into that package too. Hopefully, it’s a feature or two that’s a nice competitive differentiator and makes our part more successful in the marketplace leading to fame and a big bonus. From a performance standpoint, a chip’s clock frequency, especially in high-performance applications, is often limited by the cooling capabilities of the packaged part. Design teams that find ways to reduce W/MHz will build parts capable of running at higher clock frequencies.

In terms of quality for chips, heat is a killer. Issues like metal migration are extremely sensitive to heat. Leakage power grows exponentially with temperature, which is really bad because this is a positive feedback loop. More power causes the chip to get hotter, which causes the chip to draw even more power. If the chip is going to be designed to run hot, then care needs to be taken to increase key metal line widths, which will also increase the area of the design. More power also means more area dedicated to power and ground lines.

So taking a quick recap here, power impacts design cost, design features and performance as well as the expected lifetime and quality of the design. Is power the primary driver of your design yet?

—Barry Pangrle is a solutions architect for low power design and verification at Mentor Graphics