Next-Gen Distributed Machine Processing

By Rama Nemalikanti
The gate count increase of chip designs, especially for mobile application processor system-on-chips (SoCs), is being closely tracked to help guide the development of supporting design and simulation tools. However, sign-off quality power integrity analysis requires the inclusion of the entire integrated circuit (IC) design, along with its associated package and printed circuit board (PCB) elements, which are not needed for timing, cross-talk or design for manufacturing (DFM) analyses. The accurate prediction of power noise presence and the impact it has on package and PCB is especially critical as supply voltage continues to scale down from one generation to another, reducing the noise margin.

The size of the design in terms of the number of nodes and power integrity simulation unknowns, such as voltage in every node and current in every resistor and inductor, determines the complexity of the power integrity analyses. The number of nodes and resistors has increased at a much faster rate than gate counts, which traditionally follow Moore’s Law. In the last nine years, for some design styles the number of simulation unknowns has increased from 50M to 1.5B+, due to an increasing number of metal layers, complex metal topologies, parallel metal tracks for power/ground routing, etc. Reducing the number of design unknowns by optimizing the RLC network creation is not possible because advanced process technologies (28nm and below), require extreme levels of detail for electromigration (EM) and extraction sign-off accuracy.

Power integrity simulation coverage and analysis turnaround time is now a key concern, given the multiple sign-off requirements that exist, such as static IR, dynamic voltage drop, EM and electrostatic discharge (ESD). Sign-off analyses performed with one machine for large SoCs and ASICs can result in very long simulation turnaround times that impact design schedules.

Over the years, design tools have evolved to address the increased number of simulation unknowns. For example, technologies such as ‘smart data-caching’ allowed for the simulation of very large designs in machines with limited RAM. Multi-CPU processing support leveraged the increasing number of CPU cores available inside one machine. In addition, the hierarchical dynamic concept enabled creation and usage of sub-block models for full-chip level power noise analysis sign-off in one machine.

What is needed today are techniques such as distributed machine processing (DMP) that benefit from the increased processing power and memory space available within a private machine cluster. By distributing individual tasks over this network, considerable advantages can be achieved in runtime and memory usage without compromising the quality of the sign-off simulation. Several simulation techniques must be employed in order to maintain the fidelity of the analysis. For instance, each portion of the design should be simulated individually within the context of the whole design and the package/PCB elements. This is especially important given the ‘global’ nature of power ground noise. The use of DMP can help reduce the overall memory footprint by 3X, and improve simulation turnaround time by at least 2X.

As an example, this figure illustrates how RedHawk’s performance has evolved over two generations for a 100+M instance design. It highlights the improvements achieved from software optimizations (from RedHawk-NX to RedHawk-3DX), and from the use of hierarchical techniques (from RH-3DX_flat to RH-3DX_ERV). This evolution also shows that distributed computing reduced the turnaround time by three days with an accuracy difference of less than 1% against the original flat run on this 100M+ instance design, simulated using complex S-parameter models. Results like this can be a huge benefit for large ASIC designs.

So, as designs fabricated with advanced sub-20nm process nodes continue scaling up to 3+B simulation unknowns, employing a solution to meet the capacity, performance and sign-off requirements for next generation multi-core, multi-GHz, power-optimized designs will be key to ensuring comprehensive power noise and reliability sign-off.

—Rama Nemalikanti is a senior applications engineer at Apache Design (subsidiary of ANSYS)