Optimizing IP Management For Chiplet-Based Designs

Chiplets are making big waves in the semiconductor industry, with its global market size growing at 71.3% from 2023 to 2031. Through heterogeneous integration of multiple components of different nodes and technologies, design teams are reinvigorating Moore’s law and paving the way for designs featuring multi-billion transistors and hundreds of IP blocks.

These chiplet-based designs are as complex as they are powerful. The complexity of managing massive IPs raises crucial questions: Can design teams effectively manage this intricacy via spreadsheets? What strategies are necessary to track and search extensive IPs? And importantly, how do teams address the looming concerns of security and compliance in this new era?

Chiplet vs. Chip: What’s the difference?

A traditional chip or monolithic SoC (system on chip) is a single integrated circuit where all components are built on the same silicon die. Following the Moore’s Law, the number of transistors in a chip doubled about every two years. However, as the process technologies advance, particularly with smaller nodes (like 5 or 3 nm), the costs escalate substantially. Gordon Moore, in his 1965 paper, foresaw the end to his Law and the potential need to build large systems from smaller, interconnected functions.

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”

In contrast to traditional chips, chiplets are small, modular chips that, when connected, form a complete SoC. They can be likened to high-tech versions of Lego blocks. This approach offers numerous advantages, including enhanced performance, reduced power consumption, greater design flexibility, and cost savings. For instance, when designing a 10X10 mm chip in 3nm technology, cutting it up into four or five chiplets, most of them in a previous process node – the cost is way lower than its monolithic equivalent. This essentially means engineers can design complex chips more cost effectively and reuse IPs across different process nodes.

Key challenges in IP management for chiplets

The advent of chiplet technology provides an exciting way to extend Moore’s law while enabling design flexibility and cost reduction. However, realizing their full potential requires overcoming new challenges in design data and IP management. The days of keeping track of it on a spreadsheet are long gone – design engineers need specialized tools and scalable methodology for much deeper understanding of the characteristics, origins, and licenses of each IP.

First, a chiplet-based design can feature a diverse set of components, built on different process nodes and catering to a variety of functions. We are seeing projects grow in both sizes and complexities, which involve integrating various IPs that come from different origins, different standards, and stored in different formats. Design engineers would have to learn to operate each DDM (design data management) system to access and choose the correct versions of the IPs into their design.

After the initial selection, integrating IPs into one single chiplet-based design presents its own set of challenges. This process demands extra engineering efforts and standardization of IP tracking to ensure reliability, and seamless interaction between multiple IPs in an application-specific way. Especially for large companies that have different teams working in their own IPs or bringing third-party IPs into their own systems, it’s important to have a way to integrate all these systems together.

Finally, a rigorous verification mechanism is critical to ensure that the integrated IP blocks interact correctly and adhere to all design requirements and standards. Today’s chips could last more than 20 years, which present unique challenges verifying and maintaining these IPs over extended periods, especially as personnel changes occur over time. Issues with IP quality can lead to delays, and even failure to meet project objectives, resulting in significant financial and reputational costs.

Fig. 1: Complexities in IP management for heterogeneous integration.

One platform for IP management, reuse, and traceability

Handling exponential growth in design data and maximizing IP reuse with interoperability across EDA vendor environments is a major challenge as design teams embrace the era of chiplet.

With the acquisition of Cliosoft, Keysight has embarked on a mission to offer an easy, secure, and scalable solution that is capable of extending the IP definition to encompass a wide range of assets – silicon IPs, documents and licenses, legal contracts, scripts, and design ideas. Our IP management solution (HUB) acts as an interoperability layer that puts all these different systems and standards together. Some IP management systems are tied to specific design data management system, which causes designers wearing out each one of these operates. With HUB, it tracks all the designs and the associated data and becomes the single portal within the company to access any design within the company, making it easier for design teams to leverage and produce new IPs/SoCs.

Fig. 2: Overview of Keysight IP management (HUB) flow.

Beyond just IPs: A comprehensive lifecycle management

The tool that you use to manage your IPs no longer is useful if it’s just there to provide an IP catalog for you. you want an integrated solution that brings together different tool sets, that brings together methodology, that brings together project management features.

HUB isn’t just about managing IPs; it’s about overseeing the entire lifecycle of an IP.

First, design engineers need to be aware of where an IP comes from and the development effort that has been put into the IP, but they also want to preserve across time where and how this IP is being used to make sure that all the interested stakeholders on that IP are notified and properly informed that a new version of the IP has come along.

Second, HUB integrates not just the IPs but also the supporting documentation, similar to a bill of materials (BOM). This includes specifications, origins of the IPs, support documentation, licenses, and other materials critical to the development or reuse of the IP.

Third, as IPs evolve for new process nodes, HUB maintains the history of previous versions, ensuring traceability and clear version control. Designers can easily reference new versions for new projects while maintaining the old versions.

The perfect duo: Chiplet design meets modern data & IP management

In the dynamic world of semiconductor, the rise of chiplets signifies a major shift towards integrating heterogeneous tools, IPs, and talents that are working in the projects into complex system endeavors,

The task of searching IPs, tracking changes from previous implementations, and validating them at new process technologies has become increasingly intricate. This is particularly true in specialized markets like automotive and 5G, due to ever-evolving industry standards and design requirements.

Amidst these challenges, the role of advanced, unified IP management platforms is becoming paramount, empowering design professionals to accelerate the time-to-market, reduce development costs, and maximize the benefits of chiplet technologies. Join us on February 7 for a webinar where Keysight expert Simon Rache will delve deeper into how we’re enabling effective design data and IP management in this new era of chiplets.