Packetized Test At The International Test Conference 2021

At this year’s International Test Conference (October 10-15, 2021), Siemens Digital Industries Software is showcasing IC test and lifecycle management technologies that address the key scaling challenges facing the semiconductor industry now and in the future.

The two main topics from Tessent at ITC are:

• The rapid adoption of packetized test strategies to address design and system-scaling challenges of complex SoC designs and prepare for adoption of advanced 2.5D/3D packaging technologies.
• The unveiling of three new technologies that accelerate test and enable rapid ramping of new process technologies and product qualification.

Last year, Siemens precipitated the industry’s move from traditional DFT architectures to packetized test with the introduction of Tessent Streaming Scan Network (SSN), a full-flow implementation of packetized scan test DFT technology. Packetized test forms the foundation for effective, productive 3D IC test, along with industry standards such as IEEE 1838. Packetized test is also ideal for very large designs like those targeting artificial intelligence (AI) and other fast-growing applications.

Siemens hosts the Diamond Supporter event, which this year is focused on customer’s transition to packetized test. Attendees will hear directly from some of our industry partners, including Intel and Broadcom, about how they are leveraging SSN in their next designs. You can also hear about what’s next for this transformative technology that not only solves the problems of today, but also creates a foundation for future 3D DFT, high-bandwidth scan test, in-system test, and beyond.

New technologies
In addition to the focus on packetized test, Siemens will showcase three new DFT technologies at ITC – Reversible Scan Chain Diagnosis, Tessent SiliconInsight High Performance, and ATPG Boost – all designed to help manufacturers address timely semiconductor supply chain issues and other emerging challenges.

Reversible Scan Chain Diagnosis: Reversible Scan Chain Diagnosis is designed primarily for use in node qualification and early technology ramp, where it is proven to deliver 4x acceleration in the time required to diagnose faults. Using traditional approaches, this task can stretch to days or even weeks in the early deployment of a new process. You can learn more in this technical paper.

SiliconInsight High Performance: SiliconInsight High Performance targets new product qualification, helping to reduce time-consuming and costly characterization iterations during first silicon bring-up of new products. It improves ATPG performance of Siemens’ SiliconInsight Desktop by up to 30%, increases pin count by more than 2x to 330, and supports packetized implementations via SSN.

Tessent TestKompress ATPG Boost: The latest addition to the industry leading ATPG software is ATPG Boost. It is enhances IC test coverage and throughput in both hierarchical DFT approaches such as SSN, and traditional, flat designs. Early adopters of ATPG Boost technology are scheduled to share their experiences at the ITC Diamond Sponsorship Event and in the Siemens virtual exhibit booth theater throughout the virtual event.

For short presentations from Tessent customers and technologies, visit the Siemens virtual theater booth in the networking lounge. Topics include:

• Streaming scan network
• Re-using high speed I/Os for scan test
• Optimizing memory BIST with Shared Bus
• 3D IC DFT
• Effective IJTAG debug and visualization
• Reversible Scan Chain technology
• Defect-oriented test
• Silicon bring-up

As always, the Tessent experts are presenting session papers, tutorials, and workshops at ITC and the co-located events. For a list of those activities, visit our event page.