Pain Points At 22nm And Beyond

By Ed Sperling

The roadmap for 22nm has a giant pothole in the middle of it. That hole is supposed to be filled by extreme ultraviolet lithography, or EUV. Instead it is being patched up using immersion lithography, which is about to cause some monumental headaches for design teams.

The difference is comparable to a surgeon using a chainsaw instead of a scalpel. The cut isn’t nearly as clean, and the collateral damage will be difficult to manage. EUV operates at a wavelength of 13.5nm instead of the current 193nm.

“This will have a significant impact on the design flow,” said Jean-Marie Brunet, director of marketing for DFM products in Mentor Graphics’ Design-to-Silicon Division. “We will see more restricted designs and more regularity in verification.”

One of the best options available for manufacturing at 22nm is double patterning, but there are serious downsides to that approach. It costs more, slows down the time it takes to make a wafer, and greatly increases the cost of mask sets. All of that magnifies the cost of respins and adds to the time it takes to get chips to market.

“There are no additional tricks left for immersion,” Brunet said. “We’re now down to purely software tricks. All tuning will be done by software.”

Fork in the roadmap

But developing chips at 22nm will be a different experience for different companies. At Intel, for example, work is well underway to create 22nm chips. It’s the next node, 15nm, that makes Intel’s top architects swallow hard.

Mark Bohr, an Intel senior fellow and director of process architecture and integration, said EUV is a big missing part of the next process node, and it becomes even more critical at 15nm. He said high-k/metal gate technology also will scale well for the next couple nodes, but eventually that will require a 3D structure like a finFET or trigate.

In addition, Intel expects to use even more selective deposition and atomic layer deposition to add more precision to the manufacturing process. Bohr said Intel is well down the development of 22nm and that he is spending most of his time now at 15nm.

“We have identified viable ideas for manufacturing at 15nm,” he said. “Things are a lot fuzzier at 11nm, and we don’t know what’s going to happen yet at 8nm.”

But Intel’s roadmap is unique to Intel. A digital processor is a lot different than designs that incorporate analog components and third-party IP on a multicore SoC, which are much less predictable.

“Digital CMOS for a CPU is a lot different than an RF chip,” said Michael Buehler-Garcia, director of Calibre marketing at Mentor Graphics. “An SoC assumes that all IP is clean, so you can hit the problem first with third-party IP. Memory chips always violate the rules, and an IP block can mess up everything.”

Following that, Buehler-Garcia said there will be a lot of design rules for the glue logic, but that no one size will fit all.

Rising cost of defects and mistakes

It’s also axiomatic that as density increases, so do defects. Density is now approaching the point where designs will require extra wires and gates, and some logic to reroute signals when those defects occur. Redundancy adds costs to a design, but it makes it harder to map the interconnects.

In the past, interconnects have largely been something added to chips that were well along in the design process. Charlie Janac, CEO of Arteris, said that won’t be possible at 22nm because it’s entirely too complicated already—and redundancy will only increase the level of complexity.

“You have to be right with your design from the start,” he said. “It’s too expensive not to be. And you have to plan for two turns. By the third turn, you have to cancel the project. You can’t afford another respin. If you have a wireless application processor and you’re three months late, that will be $60 million in engineering alone. It will require more masks. And it will have an enormous customer cost, because they’re probably going to put in one of your competitor’s products.”