Partitioning For Power

By Pallab Chatterjee
Design partitioning for power in an IC is driven by which functions are on simultaneously. The new generation of “smart” power management chips introduces new constraints to the task.

Case in point: The new LP8725 from National Semiconductor. These chips have multiple DC-DC converters and both analog and digital low-dropout regulators (LDOs), with a common I2C interface for control and thermal management.

Single chip regulators mean that SoC designers have to account for peak power available, channel-to-channel matching on their power grids, data- and operation-dependent dropout on the various LDOs, and timing for the startup/shutdown of the power regulation that drives the SoC. The logic and ESL tools that work on lowering dynamic power by creating voltage islands, switched/gated power and reduced operating voltage levels make the assumption of stability and availability of these global signals. The IC tools work on the design considerations from the bond pad IN towards the logic and I/Os. And the new power management chips, due to their multi-function and multi-channel characteristics, make the design if the SoC external power source is part of the SoC design architecture.

Portable and multimedia designs have multiple modes of operation to extend battery life. The operations generally require several high current paths (600mA+), some mid-current paths (250mA+) and some low current paths. To accommodate these current levels, the SoC block partitioning needs to manage the peak current available with a tolerance, not just an IR-drop specification.

The current limits have an associated voltage dropout and absolute target limit. On the voltage targets, +/- 2% is a typical level. On the voltage dropout, levels below 200mV are considered aggressive. With target operating voltages in the 1.2v to 3.3v range, this dropout can be a significant delta in the supply. It is important to make sure that the power-down blocks have both signal tolerance to support these dropouts without either switching into the “powering down” sequence or losing information that has passed thru by reloading from non-current state retention registers.

The timing loop for power-up and power-down inside the SoC now has to accommodate “system power modulation” as additional states. To extend operational and standby time for portable devices, the various regulators can started and stopped. This function is generally controlled by state and operational logic contained in the SoC.

There are two major challenges with this design. The first is making sure data and logic that control portions of the regulator system are part of shutdown blocks that might put the design in a non-functioning mode (such as a block being turned off, which controls a regulator that is off, and not getting the control loop closed to restart one or more of the blocks). The second is the timing loop for restarting a shutdown block. The timing has to include the I/O time through the package to the board level, onto the data load and turning on of the regulator block, the stabilization of the supply, and then the completion of the block restart inside the SoC. The external portion of the loop, including the time to stabilization, can take a millisecond. This extended turn-on time may affect the transient power use in data retention and reload logic, as well as on tri-state circuitry that is waiting to turn on. These same constraints affect SoC block turn-off, as well.

If the end system, primarily portable systems, are going to use these centralized control blocks, the power grid design and application has to take into account the interconnected nature of the power rails external to the SoC. The benefits of centralized dynamic control of the application power, as well as the ability to thermally monitor the use and distribution, outweighs the added design task. These new power management chips are key drivers for low-power systems and their feature set is growing rapidly.