Electro-static discharge is responsible for 35% of all chip field failures. How do you reduce that number and effectively deal with this growing problem?
ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related.
Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher levels of digital and analog integration on the same die with several isolated and independent power and ground networks, (c) proliferation of hand-held devices resulting in more direct access to IC components, and (d) advanced package designs with tighter pitch, fewer layers, and complex shapes. Specifically, with technology migration, both gate oxide thickness and wire geometries are getting smaller, making the impact from the high current flow during an ESD event more detrimental.
This whitepaper will discuss PathFinder, a layout and circuit verification technology targeting ESD robustness and integrity. Using IP-level static and dynamic techniques and full-chip level static techniques, PathFinder can verify that a design meets ESD guidelines and identify “weak” areas of the design (layout or circuit) that are most vulnerable. It can also perform early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip. To download this paper, click here.
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