Physical Effects Affecting Design

Performing mixed-signal verification at various levels is creating a mind-bending challenge.

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With the increase in analog content in today’s designs, the industry is facing a real challenge in terms of how to perform mixed-signal verification at the functional level, at the SPICE level and down to physical implementation of the DRC rules.

Joseph Davis, product manager for Calibre interactive and integration products at Mentor Graphics, explained there are three things driving what’s happening in the need for tools in this area.

First are non-ideality or systematic effects. “There is a SPICE model that is supposed to capture all of the functionality of the transistor, but with the leading-edge technologies they’ve had to deal with additional effects that are relative to how the transistor is laid out in the design,” he explained. “It used to be that you’d draw a length and width, and you were good – you had a SPICE model.”

Now other things must be considered, as well, such as how close is it to the next device, how close is it to the well (well-proximity effects), stress effects—and these are not captured directly in the SPICE model. The layout must be done first, with the effects then calculated by the LVS tool. These are referred to as layout-dependent effects.

Next are true random effects because they imply a true variability component, which is the other side of it. “True variability—statistical variability due to variations in the fab like stress effects, litho effects, planarity effects, dopant fluctuations—that’s true variability,” Davis explained. “And that gets worse as you scale down in terms of the percentage of impact. The true variability is where you get into tools where you are looking at Monte Carlo simulations or some other way of trying to capture the impact of the random variation on the functionality of what you can expect for the chip. You guard band and so forth. And that becomes corners. In the digital world you have models for this with statistical timing analysis, but someone has to the do the characterization up front with the statistical analysis of the standard cells. How did you lay them out to account for all of the systematic effects? If you don’t take into account the systematic effects and the random effects, your circuit is not going function as you expect over the range of foundry performance.”

Also impacting the design are complexity effects. “The move to multiple voltage islands, multiple Vts, and multiple VDDs in digital designs, introduces a huge amount of complexity even in the schematic design—the architecture of the chip—when you get to implementing it, there are all these controls you have to have in place. You can’t have a single circuit that goes from low Vt to high Vt. You’ve got to have a buffer. Same thing with VDDs. Did you put it in there? In the past, there were not tools to do this kind of checking,” he added.

~Ann Steffora Mutschler