Implementing interconnects modularly enables unit-level clock gating, eliminating clock-tree switching power when no traffic is present. It also localizes logic, minimizing wire length.
The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units. This approach enables unit level clock gating, eliminating clock tree switching power when no traffic is present. Modularity also localizes logic, which minimizes long wires and further limits power consumption by keeping capacitance low. The simplicity of the protocol also allows each function to be performed with minimal logic overhead, minimizing area and leakage power consumption. This design approach is worth consideration for power sensitive SoCs.
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