Power Budgeting 101

By Aveek Sarkar
With all the processing power that is being designed into smart and superphones now, I wonder what would happen if all four multi-GHz processors were to execute simultaneously? How long would that small battery last—and would anyone be able to hold it in their bare hands?

Phone surface temperature as a function of power density.

The dilemma that processor design teams face when they plan their next-generation chip architectures is no longer limited by silicon area or library speed, but by the power they can afford to consume and the allowable heat dissipation. IC design engineers must meet maximum power specification limits in their designs to control the widening imbalance between what the system will consume versus what it can consume (figure 1). This limit, defined as a “power budget,” exists for all possible operating modes of the IC and the electronic system. IC designers must work backwards from the system level mandate of maximum allowed power consumption, system thermal tolerance, (figure 2), battery life expectation, and the component reliability point of view. They need to employ a design methodology that will allow them to accurately predict the power consumption in their system, from very early in the design process for various operating modes, while running multiple applications. The predicted power number, even though estimated at the RTL stage of the design for instance, must track what will be measured at the final gate-level netlist and eventually the silicon and system.

This methodology should allow designers to go through the RTL netlist and uncover all the potential ‘power bugs’ that pass functional testing, but which result in wasted power. This design discipline of tracking power for various operating modes of the IC will need to be adopted through the entire design cycle and through automated ‘power regression’ flows. Just like functional regression flows, various modules of the IC or the entire IC itself will be subjected to a series of vectors covering multiple application scenarios on a regular basis. That can occur weekly, for example, to identify whether the pre-defined power budget is being met and if any design changes either increased the power or introduced new ‘power bugs.’ Power consumption at the I/Os is another area of concern. Wide banks of high-speed DDR circuits continue to transmit the increasing volume of images and data that we now process in our handheld systems. This power has to be predicted and controlled through architectural and design changes in order to control the power consumption imbalance.

–Aveek Sarkar is vice president of product engineering and support at Apache Design solutions.