Power Grid Analysis—Challenges At 20nm And Below

Introduction
The need for power grid analysis (PGA) emerged in the early 2000s, when leading-edge semiconductor companies were starting 90nm designs that unveiled new technical challenges. Since then, PGA has coped with diverse challenges for each new technology node, including coverage (dynamic PGA emerged in the mid-2000s), performance, and capacity (a bottleneck at the 32/28nm node). But 20nm and 16/14nm technology nodes bring new types of challenges related to multi-patterning and FinFET technology that constrain PGA in such a way as to impact its criticality within the design flow.

PGA Before 20nm
Typical use model
Until 20 nm, PGA was mainly a perfunctory signoff step, because signoff PGA arrived way too late within the design flow to enable designers to correct major PGA-related issues, such as voltage drop or current density issues. To compensate, designers over-designed their power grid to avoid any major PGA problems popping up during the signoff analysis. Designers relied on their know-how, and past experience with previous technology nodes, but over-constraining their designs impacted their margin, as well as their routability, which led to some difficult choices. For instance, due to over-designing at 28nm, a power grid can take 30% or more of the routable space. When an area is too congested for a place and route (P&R) tool to complete its routing, designers must manually cut the grid to enable the completion of the routing.

Capacity limitation
With design sizes roughly doubling at each new technology node, existing PGA solutions ran into capacity limitations. To get around this, there are two main mitigation approaches: hierarchical PGA and design slicing. Hierarchical PGA leverages the fact that you can perform PGA on each block or intellectual property (IP) of a given design and generate a compact power model to use during the full chip analysis. Hierarchical PGA can used for highly repetitive design types such as GPU and FPGA, but cannot be leveraged for system-on-chip (SoC) designs. Design slicing is used by designers who cannot leverage hierarchical PGA. When analyzing their design, designers slice the design, run PGA on each slice separately, then merge the results. Design slicing results often contain many false errors, due to boundary effects. While both approaches have their pros and cons, as detailed in my previous article, the design constraints introduced at 20 nm and below make both of these approaches irrelevant accuracy-wise compared to a flat full chip PGA.

PGA At 20nm And Below
Double patterning
At the 20 nm node, double patterning must be used for a couple of layers to enable chip manufacturing. As long as double patterning involves only metal1 and contact/via0, there is no real impact on PGA (except for the increase in design size). Once double patterning begins affecting more layers, including some layers used for power grid definition, the impact on PGA flow becomes critical. With double patterning, late local changes to the grid to comply with decomposition requirements can have a ripple effect throughout the chip, which can affect the power grid at a stage where corrections are impractical. For that reason, the focus on upstream PGA at the floorplanning level is becoming mandatory to ensure the robustness of the power grid for a given placement.

FinFET transistors
Even though finFET transistors are mainly thought of as a front-end issue when designing standard cells, memories, or custom IP blocks, finFET construction inherently comes with specificities that impact PGA, which can force some design choices while working on a design.

Current density
FinFET transistors reduce leakage current. However, the current density in the power grid feeding these finFETs will increase, which generates additional electromigration (EM) issues for PGA. Some designers are seeing a 20% to 30% current density increase on the power grid due to finFET usage, which impacts the grid’s electromigration margin.

Performance homogeneity
Designers used to mix low-Vt and high-Vt devices within their design to balance the current draw through the power grid. When designing at 16/14nm, the high-performance low-Vt devices cannot be mixed with the high-Vt devices, which creates a concentration of low Vt or even ultra-low Vt in certain areas. This concentration clearly will overstress the power grid by creating a higher current draw in these areas, and induce voltage drop in high-Vt areas that are electrically related. Such limitations have pushed some designers to avoid ultra-low-Vt areas altogether, and reduce the low-Vt areas to the bare minimum, to prevent power analysis issues down the road.

Conclusion
PGA was an afterthought in the design flow for quite a while, as long as a simple check in the box at the signoff stage was good enough to validate that designers did a good job over-designing the power grid while delivering a working chip. With new design requirements and devices at 20nm and below, PGA must be accounted for earlier in the design flow, and designers must learn to cope with the design choices imposed by the effect of these requirements and devices on PGA. At 16/14nm and below, power becomes as critical as timing for any design implementation.