Power Intent Files Drive Low Power Adoption

By Luke Lang
“The adoption of EDA tools is actually a very slow process.” This quote by Wally Rhines of Mentor Graphics was highlighted in a red box in the June 2010 issue of EDA Tech Forum. I don’t think most of us would argue with that statement. But there are certainly exceptions to that rule, and low-power design with a power-intent file is one such exception.

The concept of a power-intent file was immediately embraced by almost everyone that was doing low-power design when it was introduced four years ago. A coalition of industry heavyweights (Power Forward Initiative) was formed in a matter of weeks. Customers were lined up ready to try the tools that supported this new power-intent file. And the best supporting evidence that this is the right way to go is the introduction of a competing standard for power-intent.

With such a strong start out of the gate it is not surprising that more than 100 low-power chips were taped out using power-intent files within the first two years. Now that we are four years into this low-power design methodology, I think it is safe to say that broad industry-wide adoption of this methodology probably occurred in the second or third year. This is quite a bit faster than the eight-year industry average that Wally Rhines said it usually took for an EDA tool or methodology to become mainstream.

Why is it that this new low-power methodology was able to beat the industry average? Again, Wally provides the answer. “In general, people do not adopt new methodologies until they have to. If they can get the job done with the methodology they have in place, they will do so.” In the case of low-power design we had a problem that was waiting for a solution. There was no methodology in place. Many designers were doing manual verification and visual inspection. The consensus was that implementation of power shutoff increases design complexity by 2 – 4 times. One can easily see that there was a serious problem when neither the design team nor the project schedule is allowed to grow by 2 – 4 times.

The new power-intent methodology for low-power design allowed designers to easily specify the power architecture and used EDA tool to do the time-consuming tasks of verification and implementation. This allowed easy migration of non-LP designs to advanced low-power architectures. Almost all of the manual tasks now can be automated because the power-intent file allows all tools to understand the power architecture.

This was exactly what the industry needed to manage the increased complexity of low-power design.

There is much that remains to be done, such as applying power intent formats to system-level design. But when it comes to mainstream RTL-to-GDSII design, we have come a remarkably long way in a very short period of time.

–Luke Lang is a senior product engineering manager at Cadence.