Power Makes IP Integration More Fun

Standards are lacking everywhere, but at least IP and EDA vendors are aware of the problems.


Remember the good old days at 130nm when it was easy to combine IP blocks on an SoC? All kidding aside, because obviously IP integration has always had its challenges, designers are experiencing new pain as process, voltage and temperature wreak havoc in bringing everything together and making sure it operates correctly, meeting all power requirements.

As I discovered, whether IP comes from within the engineer’s company or is brought in from an external source can make a big difference for the designer. External IP can be more of a ‘black box,’ which has its pros and cons. It is good in that it can make it easier to work with customers or other players in the ecosystem, but bad in that there may be no flexibility for adjustments. Internally-developed IP may give more insight into how the IP has been and can be used, but it also can be too proprietary.

As with many parts of the design flow, there are still standards lacking in this area because UPF 2.0 (IEEE P1801) and CPF can communicate design intent, but it’s not always enough for IP integration issues.

Designers need answers now in terms of balancing power and performance, hardware/software tradeoffs, and design margins.

Fortunately, the IP integration effort is in the crosshairs of IP vendors and EDA tool providers alike as they constantly seek new ways to make next-gen designs possible, and even expand services within their organizations to assist customers with such things as architectural tradeoffs, IP selection, power management techniques and more.

–Ann Steffora Mutschler

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