Power Issues In 3D

New implementation options for IP subsystems emerge as chips go vertical; so do challenges of noise and power.

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By Ann Steffora Mutschler
The challenges associated with implementing IP subsystems range from maintaining a consistent I/O voltage, achieving consistency in metal stacks to managing a clock distribution network and creating adequate isolation between subsystems on a chip. It’s enough to make your brain hurt. Add to that 3D or 2.5D stacking and the engineering considerations grow substantially.

The concept of stacking die has captivated the semiconductor industry with its promise of, among other things, better performance, shorter signal distances and in some cases a smaller footprint. But with it comes additional design complexity and cost considerations.

“In the old days when people talked about IP subsystems very often they were talking about one SoC, because within this one SoC you have IP that has certain well-defined behavior and has a good interface with protocols around it,” said Dian Yang, general manager and senior VP of product management at Apache Design Solutions. “Now the problem is that those kinds of subsystems are getting more and more complicated, so the subsystem itself becomes a gigantic chip. To be embedded inside a chip, sometimes it may not be economically feasible or may not be technically feasible in theory, especially when you look at 3D implementation.”

For example, if an IP subsystem is implemented on separate die and then stacked with the original SoC, the user interface is well-defined, a micro bump or TSV is used to connect them, But if you separate that design in order to achieve 3D, there is some disadvantage – you have two wafers, two dies, and have to use a more expensive 3D package, he said.

There are advantages, too, Yang said. “Let’s say the subsystem itself can be independently manufactured from the SoC guys in terms of the process technology: one is in 65nm and the other one can be 40nm or 28nm. The second advantage is that the testing embedded inside the 3D SoC can be a little more difficult but separately, you can do wafer-level testing much easier.”

A third implementation advantage is that if the chip can be separated into two die versus one die and uses a 3D package, sometimes the cost can actually be lower. This isn’t always true, but in some cases, especially when mixing two process technologies, the end cost can indeed be less.

“Customers may already have a subsystem implemented and well-tested – they don’t want to change anything because there is always risk associated with that…especially subsystems from a third party. For whatever economical reason they don’t want to migrate to 40 or they don’t want to migrate to 28, on the other side, if I want to shrink my whole SoC – that economically makes sense,” Yang said.

Today, RF subsystems commonly are implemented separately from the SoC because to combine them is not easy in terms of technology shrinking. Memory subsystems and IP such as embedded DRAM are also often implemented separately from the SoC as it is much more cost-effective to separate the DRAM using stacked die.

Fig. 1: Example of a contemporary audio IP susbsystem. (Source: Semico/Synopsys)

The impact of 3D on IP subsystems
Understanding the impact of 3D on IP subsystem implementation is key to moving ahead, reminded Samta Bansal, product marketing for Encounter digital implementation system, and a 3D IC expert at Cadence. “When I look at immediate implementation of 3D, I actually think about it utilizing the IP subsystems. Immediately, I see we will leverage the 3D with TSV structures as being able to use IPs and build something more, tailoring it to different applications.”

3D impacts IP subsystems on a number of fronts, including what people will actually be designing and partitioning in 3D and how to utilize the IP that is going to come from third parties. “In bringing all of this together, what becomes very important is co-design: how are you going to co-design everything together knowing that IP will come from different sources,” she explained. DFT is another area that is affected by 3D. Every chip could have its own DFT, but when put together as a system how will they talk to one another?

“There are a couple of ways to solve the challenge when you put power in the context of 3D or IP subsystems. Number one, we can solve it by adding additional resources. I can add decoupling capacitance, I can add extra vias, I can do more I/Os and increase the routing area through the power distribution network but that means cost. And the whole idea of doing 3D is to somehow manage the cost in addition to the power and performance that you would get. That is a way to do it, but is that an effective way? It depends on the application that it is targeted for, and the volume you are going to bring up, that may work and it may not work,” Bansal offered.

Good engineering always helps too, she said, pointing to Freescale’s use of stacked decoupling capacitors (decaps) instead of its standard gate oxide decaps, which shows how smart, next-generation decaps can be leveraged to realize some improvement in the clock frequency. That, in turn, helps the power network overall. IBM, in contrast, uses trench capacitors for decoupling. “You can either throw cost at the problem with more capacitance, more routing areas, more vias and try to solve the challenge of power, or you can implement these smart engineering techniques. And you can use EDA tools to optimize the power.”

Looking at power in IP subsystems from a higher level, Bansal believes the dies that are going to be farther away from the die with the connection to the package will be susceptible to noise. They will get noise from their own switching and they will be affected by the power noise from the die below it. From the pin count and routing limitations, sometimes it is very difficult to isolate the power distribution network between the two dies—both for the power and the ground supply network.

Navraj Nandra, director of analog/mixed signal marketing at Synopsys, disagrees on this point. He said the biggest challenge in terms of implementing IP subsystems that contain 3D structures is packaging and stacking up various die to make sure that the interaction of the IP functions are managed in terms of signal integrity and noise. “The idea of 3D or 2.5D actually solves a lot of these problems because the goal of 3D is to get your form factor into something that’s mobile, but what it does is reduce a lot of the trace lengths. Imagine if you had two chips communicating with each other across a board and now they are communicating with each other on top of each other through TSVs so that distance now is reduced. This actually makes the challenge from a noise perspective less because there is less distance to communicate over and the signal integrity will improve.”

Bansal doesn’t agree. “Even if you can think of these IP subsystems having their own power and ground networks unique to them, you can imagine the chip higher up in the stack will probably have more increased power noise and voltage drop because there are now a large number of metal and via layers that are added in the conduction path, and also because of the capacitance/inductance noise that must be happening from the intermediate chips. To mitigate that, design teams will not only have to focus on how to design the robust power grid on that IP subsystem, but also to ensure that the power delivery network that gets designed in other chips in that stack are also adequate to meet the system need. They can’t just worry about the design and density of the power grid routing. Now they also need to worry about the via count, the design and placement of the TSVs that are going to connect those power grid networks to the other die. That means when you are thinking about the power grid network or distribution, this co-design becomes very important.”

In all cases, this will be an interesting space to watch as IP vendors look for ways to combine their IP in unique ways. In fact, Semico Research Corp. predicts that advanced performance multicore SoC will be the device type shipping with the most IP subsystems, reaching 1.558 billion units by 2015, which is a 25% CAGR.