Power For The Masses

At 90nm, current leakage was something design teams had to consider seriously for the first time. At 65nm, they had to start thinking about various power modes. At 45nm, they had to begin seriously working on new processes, new structures, new verification approaches and a slew of proximity effects they had always assumed were someone else’s problem.

At 28nm and beyond, the problem is moving further forward. It’s now the chip architect’s problem, and at 20nm it will be an architecture team that includes hardware and software engineers all focused on the same problem—how to squeeze every bit of efficiency out of a design while minimizing the power effects.

Now it turns out that in 2.5D and 3D power may be an even bigger issue, and not just because of the thermal issues. Interposers and TSVs work as lightning rods—in fact, there are some experimental designs using mini lightning rods within TSVs. While it’s possible to use older technology in conjunction with the newest technology in 2.5D, the layers are likely to be much thinner and the physical effects will likely be much more pronounced. Add heat into that equation and there are lots of unknowns that still have to be discovered.

These are important issues to resolve, but the reality is that from here on there won’t be any simple solution. Power will have to be dealt with at every stage of the design, at every node, and probably even within derivative designs. It will be a factor in which is the best IP, how it works next to other IP, and how it gets integrated into a design. Even software will have an effect on power—both in terms of how efficiently the code uses the hardware and how well it manages the enormous number of components and states within a design.

What used to be someone else’s problem dealt with by a handful of experts has now become everyone’s problem—from architecture to modeling to IP integration to verification—and the sooner we recognize that the sooner we can really start making a dent in this problem.