Power On

By Barry Pangrle
Process development is more challenging at each successive technology node but the march forward, for the time being, continues unabated. Voltage scaling stopped around the 100nm node at roughly 1.0v as threshold voltages stopped shrinking in an attempt to keep leakage in check. It’s been the progression to the newer and smaller technology nodes that has really pushed power to the forefront of the design process.

TSMC released its quarterly results at the end of October and it’s clear that the demand for the new process nodes from TSMC’s perspective isn’t slowing down—60% of TSMC’s revenue is now coming from technologies below 100nm. The percentage revenue curve seven quarters in for 40nm looks very close to the 65nm curve at the same point into its rollout: 17+% vs. 18%, respectively. If the trend continues, we should expect to see 40nm revenue surpassing 65nm revenue in the next few quarters (note that 65nm passed 90nm twice before staying in front).

As more designs cross the 100nm barrier, the need for designing in power management just keeps increasing. David Manners has quoted TSMC’s European president, Maria Marced, as saying, “By the second half of 2011, 28 nm will be 2% of our revenues.” TSMC claims 71 production tape-outs on 28nm in the pipe for between now and 2012. Again, there are no signs of the progression to newer technology nodes slowing down, at least from a volume standpoint. It should also be noted that TSMC’s revenue also has increased during this time period from NT$69.24 billion to NT$112.25 billion.

While the use of high-k metal gate (HKMG) technology helps with leakage, it is not a panacea. To put it all into perspective, if the voltage scaling for Vdd that followed from 0.5 um (5v) to 100 nm (1v), then 28nm Vdd should be in the vicinity of 0.28v. Even if nominal Vdd drops to 0.85v that would still be over three times that of the scaled voltage and many 28nm processes will likely still operate at close to 1.0v. The foreseeable future uses more complex power management schemes to enable designers to get the most out of these smaller nodes.

–Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.