The Race For Better Verification

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis using static analysis. Static analysis is a mix of structural and formal techniques that let designers focus on verification and not on customizing the tool to attack a problem area.

Besides raw speed, and capacity, the newest tools are addressing the data management for sign-off of these SoCs. Smart reporting and assisted debug is a key requirement otherwise designers and verification teams will drown in a flood of analysis results. All of this innovation and targeted investment will be making SoC sign-off manageable, if not easier.

Ascent IIV is an automatic RTL verification tool. Since no testbench is needed, it is an efficient method to find RTL bugs earlier in the design flow before they become more expensive to uncover. It finds bugs using a hierarchical analysis of design intent. The analysis tries to distinguish what is the root cause for issues to minimize debug time.  When the tool is launched, Ascent IIV performs a comprehensive analysis of each of the design elements in the RTL code to generate functional assertions or what we call intent checks. These intent checks are then analyzed by an array of engines to verify a design’s functional behavior.

Like other automatic formal tools in the marketplace, Ascent IIV handles a wide  range of intent checks:

• FSM deadlocks and unreachable states
• Bus contention and floating busses
• Full- and Parallel-case pragma violations
• X-value propagation
• Array bounds
• Constant RTL expressions, nets & state vector bits
• Dead code
• Uninitialized memory

In the following table you will see the results of the analysis of Ascent IIV on 130K gates of RTL logic.

Table 1.  Ascent IIV Intent Checks and Failures Report for a 130K Gate Block.

The tool generated 31,186 intent checks (assertions) that were analyzed by its various engines and 2,999 failures were produced in total.  The hierarchical reporting of the tool characterized these failures into several categories.  It determined that by fixing the Primary Errors (purple column in the table) this would eliminate the duplicate, secondary and many structural errors.  In this benchmark, 181 primary errors were identified.  This represent a dramatic contraction of almost 95% of the total failures from the tool.

Smart reporting is a now an important and necessary component of RTL verification and SoC sign-off.  With the ever growing complexity of verification we need more leverage in finding and fixing those errors that will make the biggest impact on design quality.