Reaching The Breaking Point

A survey on timing constraints turns up some interesting trends—and solutions.

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By Ron Craig
Atrenta recently conducted a user survey on timing constraints, in an effort to find out more about how they are being managed and where the issues are. I expected a diverse range of feedback on different use models, roadblocks etc., but it was very interesting to see some trends pop up:

  1. 94% of respondents said that timing constraints were a problem.
  2. About 30% of respondents noted that bad timing constraints had resulted in silicon failure, and about 60% said bad constraints had resulted in tapeout delays.
  3. 70%-plus said they planned to simply “try harder” during their next project to avoid these problems, with no plans to use any kind of automated verification or management techniques.So even though timing constraints are enough of a problem to be killing chips, most design teams are continuing to follow the same practices that have failed them in the past—in the hope that things will somehow get better!

ostrichThe survey also collected details on the approaches that design teams are taking today, which turn out to be a mixture of manual review and waiting to see what their backend tools complain about.

As I reviewed the numbers, I concluded that either we (the EDA industry) are failing to get the message across that better solutions exist, or design teams are somehow deluding themselves. It’s clear to me from discussions with a broad range of customers that the biggest competitor for any kind of automated timing constraint verification and management solutions (Atrenta’s included) is the user who believes that they have everything under control. Maybe timing constraint management is the schematic entry of chip design? The old solutions may have worked in the past, but they stopped scaling a long time ago.

When it comes to investigating potential solutions, design teams tend to have a laser focus. The question I’ll frequently hear is: “My last chip died due to a problem with XYZ. Would your tool have caught it?”

Unfortunately I’m not a good enough planner to carry around a hundred variants on my product pitch, so over the years I’ve learned that listening is the most important skill. Even though we offer a range of solutions proven to catch chip killers, the customer may only hear us talk about one – the one that they care about.

It’s naturally tempting to focus on preparing for known problems, but what about the unknown ones? Despite their best intentions, designers leave landmines in their designs all the time, issues which may only be triggered when moving to a new technology node. The evidence is mounting that when it comes to timing constraints, we’re reaching a breaking point where the old techniques aren’t working anymore. A customer of ours noted that a recent design of theirs had more than a million lines of timing constraints, but they actively minimized risk by employing our solutions to catch constraint issues before they became problems. Their approach has its roots in lessons learned from past failures, failures that their business can’t afford to repeat.

It’s clear that when it comes to timing constraints, the old ways aren’t working anymore. The time has come to start looking for problems before they become expensive problems.

–Ron Craig is senior marketing manager at Atrenta.


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